Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Yukimasa Minami

Jun Osanai

Kazutoshi Ishii

Yuichiro Kitajima

Miwa Wake

Keisuke Uemura

Fumiyasu Utsunomiya

Yoshifumi Yoshida

Kotaro Watanabe

Masaru Akino

Yoichi Mimuro

In an ESD protection element configured to protect a semiconductor device, a first N-type low concentration diffusion layer is formed, as an offset layer for easing electric field concentration, under a LOCOS oxide film formed at each end of the gate electrode, and a second N-type low concentration diffusion layer and a third low concentration diffusion layer are formed under an N-type high concentration diffusion layer on the drain side to set the point of breakdown at a level deep inside a substrate from a surface of the substrate. The hold voltage is thus raised to a voltage equal to or higher than the operating voltage and a noise can be relieved without increasing the element size of the ESD protection element even when the noise having a large amount of positive electric charge is applied to a Vdd supply terminal.

Semiconductor device

All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type polycrystalline silicon and connecting the same in parallel or in series. The respective resistors themselves cancel a stress received from a resin upon packaging of the resistance voltage dividing circuit since the N-type polycrystalline silicon and the P-type polycrystalline silicon respectively indicate a shift amount in a reverse direction with respect to a stress. There can hence be provided a resistance voltage dividing circuit in which a variation in voltage division ratio at packaging is reduced than before.

Semiconductor device having resistance voltage dividing circuit

A semiconductor integratd circuit device includes fuse elements formed on an element isolation insulating film, and an insulating film, an interlayer insulating film and a silicon nitride film successively formed over the fuse elements. An opening region extends through the silicon nitride film into the interlayer insulating film above the fuse elements, and openings formed in the interlayer insulating film are positioned on both sides of middle portions of the fuse elements. The openings facilitate blowing off of the insulating film during laser cutting of the fuse elements, reducing physical damage to the element isolation insulating film under the fuse elements.

Semiconductor integrated circuit device

Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.

Flip-chip mounted semiconductor device

A semiconductor device includes a semiconductor substrate, a body region, a body contact region and a cancelling region each of the first conductivity type, and a buried layer, an epitaxial layer and a source region each of the second conductivity type. A trench is provided in the epitaxial layer from a surface thereof. A gate insulating film is provided on an inner wall of the trench, and a gate electrode made of polycrystalline silicon is in contact with the gate insulating film and fills the trench. The cancelling region, which is provided below a bottom surface of the trench for cancelling a conductivity type of the buried layer, has a distribution center located below a boundary surface between the buried layer and the epitaxial layer. A trench bottom surface lower region of the first conductivity type is provided from the bottom surface of the trench continuously to the cancelling region.

Semiconductor device and method of manufacturing the same

In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.

Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region () is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region () is depleted, thereby increasing the breakdown voltage in the OFF state.

Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.

Method of manufacturing a semiconductor device

Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.

Semiconductor integrated circuit device and manufacturing method thereof

A current mirror circuit has a first MOS transistor to which an input current is supplied. The first MOS transistor has a gate formed of polysilicon. A second MOS transistor has a gate formed of polysilicon and connected directly to the gate of the first MOS transistor via a polysilicon layer for producing an output current whose magnitude is a magnitude of the input current multiplied by a current mirror ratio. A fuse has one terminal connected to a gate portion between the gate of the first MOS transistor and the gate of the second MOS transistor and another terminal that is grounded.

Current mirror circuit

A Provided is an electronic device in which: alternating current power from an RF coil which receives an electromagnetic wave and converts the electromagnetic wave into power is rectified by a diode and a first capacitor; the power is stepped up by a charge pump type step-up circuit; the power stepped up by the step-up circuit is stored in a second capacitor by a charging and discharging circuit; and the stored power is supplied from the charging and discharging circuit to an RF transmission circuit.

Electronic device

In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

Method for manufacturing semiconductor device

In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.

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Chiba, Japan

Yukimasa Minami