Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Other

Yukiko Umemoto

Toshihiro Tanaka

Yutaka Shinagawa

Takashi Yamaki

Hiroyuki Tanikawa

Mitsuru Hiraki

Nozomu Matsuzaki

Yoshiaki Kamigaki

Shinichi Minami

Kozo Katayama

Masamichi Fujito

Kazufumi Suzukawa

Akira Kato

Jiro Ishikawa

A semiconductor device includes a plurality of nonvolatile memory cells (). Each of the nonvolatile memory cells comprises a MOS type first transistor section () used for information storage, and a MOS type second transistor section () which selects the first transistor section. The second transistor section has a bit line electrode () connected to a bit line, and a control gate electrode () connected to a control gate control line. The first transistor section has a source line electrode () connected to a source line, a memory gate electrode () connected to a memory gate control line, and a charge storage region () disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc&#x3c;tm.

Semiconductor device

An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

Semiconductor data processing device

Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed

This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC among flash memory cells MC to MC formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL in which the memory cell MC is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL . As a result, parasitic capacitances Ca and Ca generated between p type wells PWL and PWL in which the unselected memory cells MC and MC are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.

Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system

Growing community of inventors

Kodaira, Japan

Yukiko Umemoto