Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubihsi Denki Kabushiki Kaisha

Yukiko Maruyama

Takashi Itou

Mikio Asakura

Seiji Sawada

Yasuhiko Tsukikawa

Yutaka Ikeda

Kyoji Yamasaki

An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.

Semiconductor memory device having select circuit

In response to an output data width switching mode signal, a predecoder zone&plus;selector zone outputs selection signals SEL to SEL and WORDA to WORDC to a preamplifier&plus;write driver zone. The preamplifier&plus;write driver zone can switch connection between global I/O lines GIO< > to GIO< > and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Semiconductor memory device capable of switching output data width

This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.

Semiconductor memory device that operates in synchronization with a clock signal

A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.

Synchronous semiconductor memory device performing data output in synchronization with external clock

A semiconductor integrated circuit includes a DLL circuit generating an internal clock signal, a plurality of clock generators generating respective output clock signals based on the internal clock signal, a plurality of output buffers outputting to a plurality of data input/output pins data according to corresponding output clock signals respectively, and a selection circuit. The selection circuit outputs a code signal for allowing the timing of the earliest output clock signal to conform to the timing of the latest output clock signal. A predetermined clock generator adjusts the timing of the output clock signal according to the code signal.

Semiconductor integrated circuit having circuit for correcting data output timing

A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.

Growing community of inventors

Hyogo, Japan

Yukiko Maruyama