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Renesas Technology Corp.

Yukikazu Matsuo

Tetsushi Tanizaki

Masami Nakajima

Yoshihiro Nagura

A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter holds the number of repetitions of a repeat sequence that is prescribed by the program. The up counter holds a PC value that is counted up for each clock pulse. The selector selects, as a PC value to be output next, the post-jump PC value or the value that is held by the up counter. The logic circuit refers to the output value of the program counter and the output values of the registers and the down counter, and generates a signal that instructs the selector what PC value should be selected as the next output value.

Program counter circuit

A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Test pattern generation circuit and method for use with self-diagnostic circuit

When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes. Therefore, because the for-synchronization-circuit enabling signal is not received from the outsides but is produced, a circuit area of a semiconductor integrated circuit can be efficiently used.

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Hyogo, Japan

Yukikazu Matsuo