Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Hitachi Tohbu Semiconductor, Ltd.

Yukihito Ishihara

Kazuo Yamakido

Yuko Tamba

Takao Okazaki

Katsuhiro Furukawa

Masaru Kokubo

Yasuyuki Kojima

Yoichiro Kobayashi

Yasuyuki Kozima

Yasushi Yokosuka

Kazuhiko Takaoka

Hirotaka Hara

Masanori Otsuka

Norimitsu Nishikawa

Taiji Kondou

Atsushi Mizuno

Takeshi Shimanuki

Digital demodulators for phase modulated and amplitude-phase modulated

The number of current sources and switches necessary for a plurality of unit D/A converters using equal reference currents, are drastically reduced to reduce the parasitic capacitance coupled to current output lines, by converting a plurality of digital signals of a predetermined bit, which are divided from an input digital signal, into an analog current unit D/A converters and by converting the analog current in a manner to correspond to the weights of the corresponding input digital signals, thereby to synthesize the currents. The fixed reference digital signal is inputted to the D/A converter for cancelling offsets. The offsets of a plurality of analog output signals in positive and opposite phases obtained by branching the output of the D/A converter are individually detected. After this, the DC offset values of the individual analog outputs are used as offset adjusted negative feedback signals for a desired value. One of them is the digital signal to be fed back to the input portion of the D/A converter whereas the other is the analog signal to be fed to a path portion obtained by branching the output of the D/A converter.

Converter, offset adjustor, and portable communication terminal unit

A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

Phase demodulator receiving inputs from phase detector and binary phase

The difference between the output current of a voltage-current converter circuit and the output current of a local D/A converter circuit 2, whose output current is controlled by a feedback signal, is integrated by an analog circuit of which one end is connected to a DC potential point, and the voltage obtained by the integration thereof is quantized by a quantizing circuit. The result is integrated by a digital integrating circuit and is fed to a feedback correcting circuit 6 and, further, the result of A/D conversion is output. The feedback correcting circuit outputs a temporary feedback signal while the digital integration is being operated based on the output of the quantizing circuit. After the digital integrating operation completes the digital integration operation, a corrected feedback signal is generated instead of the temporary feedback signal. The signals inputted into the analog circuit 3 are continuously sampled even while the digital integration operation is being carried out.

Analog/digital converter of the over-sampling type with feedback

A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

Running-average/decimation filter for an oversampling A/D converter

In a MODEM having modulation and demodulation circuits and a circuit for controlling the modulation and demodulation, a modulator-demodulator apparatus includes a register for accepting a macro-instruction from an external source; a circuit for interpreting and executing the macro-instruction; and a circuit for outputting a response to the macro-instruction, whereby the MODEM is controlled in response to the macro-instruction accepted from the outside source. The modulator-demodulator apparatus is suitably integrated over a single semiconductor substrate.

Modulator-demodulator apparatus and system

In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Synchronism is thus established and maintained between the circuit and the external device.

Synchronizing system

Growing community of inventors

Ohme, Japan

Yukihito Ishihara