Toyoda Gosei Co., Ltd.

Kabushiki Kaisha Toyota Chuo Kenkyusho

Yukihisa Ueno

Toru Oka

Tohru Oka

Nariaki Tanaka

Masayoshi Kosaki

Takahiro Fujii

Takaki Niwa

Kazuya Hasegawa

Kota Yasunishi

Tsuyoshi Nomura

Toshiyasu Ito

Takeshi Miyazaki

Tomoyoshi Motohiro

Hiromitsu Takeuchi

Junya Nishii

Atsuto Okamoto

Tsutomu Ina

Naoto Kuriyama

Masahiro Hanazawa

Tadashi Ito

An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.

Method for producing semiconductor device

To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region. In the groove forming process, the groove that penetrates the p-type semiconductor layer and has a bottom portion located in the first n-type semiconductor layer is formed. In the first electrode forming process, the first electrode is formed on an insulation film on a surface of the groove.

Semiconductor device and method for manufacturing the same

An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 &#x3bc;m to 1.6 &#x3bc;m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 &#x3bc;m to 1.6 &#x3bc;m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

Semiconductor device

To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.

To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage.

Semiconductor device including a mesa groove and a recess groove

The method for manufacturing comprises an ion implantation process of implanting a p-type impurity into a semiconductor layer mainly made of a group III nitride by ion implantation; a first heating process of heating the semiconductor layer at a first temperature in a first atmospheric gas including ammonia (NH) after the ion implantation process; and a second heating process of heating the semiconductor layer, after the first heating process, at a second temperature that is lower than the first temperature in a second atmospheric gas including oxygen (O).

Semiconductor device, method for manufacturing the same and power converter

An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.

Semiconductor device and method for manufacturing semiconductor device

A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A protective film is formed so as to continuously cover a side surface and a bottom surface of the step. A field plate electrode connected with the p-electrode is formed on the protective film. When a distance from the pn junction interface to the surface of the protective film on the bottom surface of the step is defined as h (&#x3bc;m), a dielectric constant of the protective film is defined as &#x2208;, and a thickness of the protective film at the pn junction interface on the side surface of the step is defined as d (&#x3bc;m), (&#x2208;&#xb7;h)/d is 4 or more, and &#x2208;/d is 3 (1/&#x3bc;m) or more.

A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to coat the semiconductor layer; and an electrode provided to have electrical conductivity and configured to form a Schottky junction with the semiconductor layer. The protective film includes: a first layer made of AlOand arranged adjacent to the semiconductor layer; a second layer made of an electrical insulation material different from AlOand formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The electrode is located inside of the opening structure.

A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of AlOand arranged adjacent to the p-type semiconductor layer and the n-type semiconductor layer to coat an edge of a p-n junction surface; a second layer made of an electrical insulation material different from AlOand formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The gate insulating film is placed inside of the opening structure.

An antenna device is provided with a first connecting electrode, a first tunnel diode, a first antenna member and a fixed electrode. The first connecting electrode is configured to be connected to a fixed potential via a load. The first tunnel diode has a pair of electrodes. One of the electrodes of the first tunnel diode is connected to the first connecting electrode, and the other electrode of the first tunnel diode is connected to the first antenna member. The first antenna member has a conductive property and includes a first portion and a second portion. The first portion of the first antenna member is connected to the other electrode of the first tunnel diode. The fixed electrode is connected to the second portion of the first antenna member. The fixed electrode is configured to be connected to the fixed potential.

Antenna devices

A dielectric actuatorof the present invention has a structure in which an elastic, high-dielectric material portionis held by elastic insulating material portionsandand the elastic insulating material portions are held by electrodesandfrom the outside. A base material for the elastic, high-dielectric material portionis formed of a silicon rubber and a graphite powder is mixed therein to apply a conductive property.

Growing community of inventors

Kiyosu, Japan

Yukihisa Ueno