Sharp Kabushiki Kaisha Corporation

B.e. Technology Co., Ltd.

Yukihiro Yoshida

Akira Tanimoto

Noboru Kubo

Satoshi Tominaga

Toshiyuki Maegawa

Toru Izaki

Shintaro Hashimoto

Toshio Yamagishi

Naoyuki Fukuda

Kunihiro Katayama

Sunao Katoh

Kazuo Kinosita

Sanao Katoh

Mitsuo Tada

Shizuka Hiraike

A computer device includes a processor for processing an object code containing a plurality of instruction words. It further includes a memory for storing a plurality of pseudoinstruction words respectively corresponding to the plurality of instruction words. Preferably, the number of bits of each of the plurality of pseudoinstruction words is less than that of each of the plurality of instruction words. Finally, the computer device includes an instruction word converter for converting the pseudoinstruction word read out from the memory into an instruction word of the object code, and for outputting the instruction word obtained by the conversion to the processor.

Computer device and method for processing data utilizing

A power control apparatus for controlling power used by a digital electronic device having a plurality of processing devices for example, a CPU and a plurality of I/O controllers as well as a memory for storing power control instructions. The CPU is configured to output power control signals via one of the I/O controllers based on the signals or power control instructions. A microcomputer is provided to which the power control signals are input and which are configured to control power and clock frequency supplied to each one of the plurality of processing devices based on the power control signals. The microcomputer detects the input of the power control signal, sets power control bits for the plurality of processing devices into a data register based on the detection, and outputs via the I/O port the contents of the data register to control the power to each of the plurality of processing devices.

Power control apparatus for digital electronic device

A digital data processing apparatus comprising a memory and a central processing unit. The digital data processing apparatus includes a code conversion section. The code conversion section assigns a virtual code for a duplicate code and converts the virtual code into a real code. The memory may consist of an external memory, and the external memory may include the code conversion section. The apparatus also comprises a code inverse section which converts an instruction to an address which is outputted to a memory through a data transmission path.

Apparatus for instruction-word-linK compression

An apparatus for controlling electric power used by a digital electronic device. The apparatus includes a read only memory for outputting a coded electric power management order, and an address counter connected to the read only memory for accessing the read only memory. In addition, the apparatus includes a control order register connected to the read only memory for storing the coded electric power management order output from the read only memory. A control decoder is connected to the control order register for decoding the coded electric power management order stored in the control order register and for outputting a micro-order therefrom. Also included is the apparatus in a group of registers connected to the control order decoder for storing and processing the electric power control management order decoded by the control order decoder.

Power control apparatus for digital electronic device, processing

The high speed semiconductor memory includes at least one memory module and a cache controller. The at least one memory module includes a plurality of memory cells for storing data and a cache memory for storing part of the data stored in the plurality of memory cells, The cache controller includes a hit ratio counter for obtaining an average cache hit ratio and a comparator storing a desired threshold hit value and comparing the average cache hit ratio with the desired threshold value. The cache controller determines whether data corresponding to an input address are stored in the cache memory and allows to readout such data from the cache memory, otherwise controlling the read-out of data from the plurality of memory cells for storage in the cache memory so as to update the contents of the cache memory. A request signal for transferring data from the memory cells to the cache memory is generated when the average cache hit ratio is lower than the desired threshold value. The high speed memory further includes a prediction controller for selecting data to be transferred from the memory cells to the cache memory.

High speed semiconductor memory including a cache-prefetch prediction

A multi-functional operating circuit provides a flexible architecture for dynamically or statically changing plural operating functions in a manner to complex the operating units needing the fastest speed, prevent an electric delay of a signal or be integrated at higher density. The multi-functional operating circuit includes plural operating circuit units having any-valued adding unit, subtracting unit, multiplying unit, squaring unit and logical operating unit, and plural instruction decoders for dynamically or statically selecting plural operating units for controlling a selected combination of these operating units in response to micro orders derived from external instructions in a manner to apply to the necessary operating function.

Multi-functional operating circuit providing capability of freely

A multivalued adder for processing addition of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input circuit includes parallel inputs for binary logic and multivalued logic, and receives the first data. The first input circuit also outputs a first set of bit data representing the first data. Similarly, the second input circuit includes parallel inputs for binary logic and multivalued logic, and receives the second data. The second input circuit also outputs a second set of bit data representing the second data. An adding circuit, connected to the first and said second input circuits, adds the second set of bit data and the first set of bit data. An output circuit, connected to the adding circuit, converts the output of the adding circuit into data in binary logic and multivalued logic, in parallel, and outputs converted data in binary logic and multivalued logic, in parallel.

Multivalued adder having capability of sharing plural multivalued signals

A multivalued subtractor for processing a multiplication of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input circuit includes parallel inputs for binary logic and multivalued logic, and receives the first data. The first input circuit also outputs a first set of bit data representing the first data. Similarly, the second input circuit includes parallel inputs for binary logic and multivalued logic, and receives the second data. The second input circuit also outputs a second set of bit data representing the second data. A subtracting circuit, connected to the first and said second input circuits, subtract the second set of bit data from the first set of bit data. A output circuit, connected to the subtracting circuit, converts the output of the subtracting circuit into data in binary logic and multivalued logic, in parallel, and outputs converted data in binary logic and multivalued logic, in parallel.

Multivalued subtracter having capability of sharing plural multivalued

A multivalued multiplier is arranged to treat a plurality of multivalued signals at one time without having to increase the circuit scale. The multivalued multiplier includes a logic circuit and a multivalued circuit connected to the logic circuit. The logic circuit serves to receive two or more signals and output a predetermined logic result. The multivalued circuit serves to process the predetermined logic result and output a predetermined multivalued signal.

Multivalued multiplier for binary and multivalued logic data

An apparatus for transmitting information with a reduced number of bits without decreasing a transmission speed of a serial-signal and without omitting any information in the serial-signal includes an encoding unit (20) for encoding a serial-signal with binary-value into a serial-signal with quaternary-value and for outputting the encoded serial-signal with the quaternary-value, and a decoding unit (30) for receiving the encoded serial-signal with the quaternary-value output from the encoding unit (20) and for decoding the received serial-signal with the quaternary-value into the serial-signal with the binary-value.

Serial-signal transmission apparatus

A central processing unit comprises a bidirectional circuit for converting a binary data and a binary address supplied from a binary logic circuit in the CPU into n-valued (n is an integer of 3 or larger) data and an n-valued address, respectively, and transmitting converted signals to the outside, and for converting n-valued data and an n-valued address supplied from the outside into binary data and a binary address, respectively, and transmitting converted signals to the binary logic circuit.

Central processing unit including two-valued/n-valued conversion unit

A divide circuit which is adapted to obtain a quotient by using a dividend and a divisor, the dividend and the divisor being input signals of either quadruple logic or quadruple logic converted from binary logic, includes a unit for setting a candidate value of the quotient, a unit connected to the setting unit for multiplying the quotient candidate value by the divisor, and a unit connected to the multiplying unit for comparing a result obtained by the multiplying unit with the dividend.

Divide circuit having high-speed operating capability

An adder including a subdividing unit for subdividing an addend and an augend formed in plural bits into bit groups each having a specified number (an integer of 2 or larger) of bits, and an addition unit for executing parallel addition for each of the bit groups. The addition unit is arranged such that the addend and the augend are added together for each bit when they are represented in multivalued logic having three or more steps of logic values.

Adder for reducing carry processing

A square-root operating circuit performs square-root at high speed and applies to both a binary signal and a quadruple signal. The square-root operating circuit includes X.sup.2 circuits, the performing unit, and adding circuits. The X.sub.2 circuits performs a square of an input signal. The performing unit is arranged to perform the square of a candidate square-root of any one of an originally quadruple logic input signal and a quadruple logic input signal converted from a binary logic. The adding circuits compare the input signal with a square of a candidate square-root at each digit and output a result of the comparison so as to discriminate a proper digit of the square-root.

Square-root operating circuit adapted to perform a square-root at high

A multiplier, which is capable of processing a multiplication of multi-valued data, includes a register transforming circuit (RC) for shifting data stored and outputting a plurality of data, a multiplying circuit connected to the register transforming circuit (RC) for multiplying the outputs from the register transforming circuit (RC) and an adding circuit connected to the multiplying circuit for adding the multiplied results according to a predetermined arithmetic rule based on logic to be used. The multiplier further includes an AND circuit element connected to the adding circuit for shifting and sending out the outputs from the adding circuit. A W register is connected to the adding circuit for storing the shifted outputs from the adding circuit according to the AND circuit element, and a further AND circuit element is connected to the W register for shifting and sending out the outputs from the W register. Another AND circuit element is connected to the further AND circuit element for further shifting the outputs from the further AND circuit element. Finally, a W register is connected to the further AND circuit element for storing the shifted output from the W register.

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Ikoma, Japan

Yukihiro Yoshida