Kabushiki Kaisha Toshiba

Yukihiro Urakawa

Masataka Matsui

Takashi Inukai

Atsushi Kawasumi

Natsuki Kushiyama

Takeo Maeda

Hiroshi Momose

Koichi Kinoshita

Takeshi Yoshida

Yukihiro Fujimoto

Naoki Kiryu

Naoyuki Tamura

Fujio Ishihara

Tsukasa Shirotori

Shinji Kitabayashi

Hiroto Fukuhisa

A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.

Semiconductor integrated circuit

A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.

Stacked-chip device

A system in package device according to an example of the present invention includes a package substrate, an external terminal which is arranged on one face side or the other face side of the package substrate, a first chip which is arranged on the other face side of the package substrate, a second chip which is arranged on the first chip, and bumps which are arranged between the first chip and the second chip. A signal to be input into the external terminal is input into the first chip via the second chip.

System in package device

A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit.

Semiconductor device, semiconductor package and memory repair method

A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.

Semiconductor integrated memory circuit and trimming method thereof

The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and the voltage applied to the second power supply terminal is returned to the second potential. When stress is generated in the first to fourth transistor included in the first or second inverter, the potential difference between the first power supply terminal and the second power supply terminal is made larger than a difference between the first potential and the second potential.

Semiconductor memory device and trimming method thereof

A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.

In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4&#xd7;i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.

Memory chip and semiconductor device using the memory chip and manufacturing method of those

A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second field effect transistors, fourth and fifth field effect transistors serially connected between the first and second power source terminals, and a sixth field effect transistor having a gate connected to the word line and used for data transfer between a second bit line and the drains of the fourth and fifth field effect transistors. The threshold voltages of the first and fourth field effect transistors are different from each other and the magnitude relation thereof is determined according to ROM data.

Programmable ROM

The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.

Semiconductor integrated circuit wiring design method and semiconductor integrated circuit

An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.

Upper-layer metal power standard cell

A thermal management system according to an embodiment of the present invention includes first and second thermo sensors embedded in a chip, a trimming control circuit which determines a characteristic of the first thermo sensor based on a trimming value, a nonvolatile memory which stores trimming data relating the characteristic of the first thermo sensor in an initial state and a system controller which provides temperature data to the trimming control circuit, wherein the temperature data relates a chip temperature detected by the second thermo sensor, wherein the trimming control circuit updates the trimming value based on the temperature data and the trimming data.

Thermal management system

Chip on chip device including basic chips capable of functioning independently from each other, and a system in package device including the chip on chip device

A semiconductor device has a semiconductor element connected to an input/output terminal and a reference voltage terminal, a first rectifier element connected between the input/output terminal and the reference voltage terminal, which performs rectifier operation to prevent a voltage of the input/output terminal from becoming higher than a voltage of the reference voltage terminal by a predetermined value or more, and a second rectifier element connected between the input/output terminal and the reference voltage terminal, which performs rectifier operation to prevent the voltage of the reference voltage terminal from becoming higher than the voltage of the input/output terminal by a predetermined value or more.

Growing community of inventors

Kawasaki, Japan

Yukihiro Urakawa