Hitachi, Ltd.

Hitachi Keiyo Engineering Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Nhk Spring Co., Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Chubu Software, Ltd.

Hitachi Ulsi

Yukihiro Seki

Ryuichi Hattori

Tsunehiro Tobita

Kunihiro Katayama

Takashi Totsuka

Takashi Tsunehiro

Takeshi Suzuki

Takeshi Wada

Kenichi Kaki

Jun Kitahara

Hajime Yamagami

Takashi Kikuchi

Takao Okubo

Shigeru Kadowaki

Masamichi Kishi

Manabu Saito

Yosio Takaya

Shigemi Adachi

Koichi Okazawa

Nobukazu Kondo

Masaya Umemura

Takashi Moriyama

Hideyuki Osakada

Kouichi Nakai

Shinichi Suzuki

Hideki Osaka

Tomohisa Kohiyama

Hiroshi Mizukami

Hiromichi Itoh

Shigeo Tsujioka

Ichiro Ote

Jun Umeno

Takashi Shimojo

Yuji Miyagawa

Yoshiaki Kitazume

Shigeru Sakurai

Hiroshi Mochizuki

Kuniaki Kawahara

Junichi Taguri

Shigeru Murasaki

Toshinobu Matsuoka

Michiyuki Suzuki

Toru Itihara

A stabilizer device includes a stabilizer extending in a width direction of a vehicle, and a bush unit. The bush unit includes a bracket formed of metal, and a rubber bush. The rubber bush is formed of a plurality of bush pieces, and is fixed to the stabilizer by an adhesion layer. The adhesion layer is constituted of an adhesion member including an adhesive applied to inner surfaces of the bush pieces. A bonding display portion formed of a part of the adhesion member is provided at a corner on an end face of the bush piece.

Vehicle stabilizer device

In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.

Interface switching apparatus and switching control method

A page table on a main storage contains a correspondence between guest virtual address and a host real address, and a TLB in a processor holds said correspondence calculated by a previous address translation. A PTBR holds a real address of a page table. When a processor detects a TLB purge, the processor starts a host when detecting a TLB purge. The host examines a virtual space change processing executed by the guest, and stores a correspondence between a new guest virtual address and a new host real address in the page table.

Information processing apparatus and memory control method

Information processing system, bus arbiter, and bus controlling method

A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Flash memory control method and apparatus processing system therewith

A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.

Bus system

A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Flash memory control method and information processing system therewith

An information processing apparatus includes a plurality of processor boards arranged parallelly on the main board and the DC--DC converters for generating operation voltages for processor devices each disposed between the adjacent processor boards. Further, a metal plate with high thermal conductivity is placed in close contact with an area of each of the processor boards where devices generating a large amount of heat are mounted. Heat dissipating fins are joined to the surface of each of the metal plates so that when the processor boards are mounted on the main board, the heat dissipating fins do not contact the DC--DC converter. The heat dissipating fins and the DC--DC converters are arranged so that they are vertically disposed one over the other with respect to the main board.

Information processing apparatus, method of arranging components of the

An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.

Method and system for arbitrating a bus according to the status of a

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Information processing system

In an information processing apparatus including a backboard having a bus for transmitting signals therethrough, at least one module, and a connector to connect the bus to the module, the backboard includes two terminators disposed respectively at both ends of the bus for providing matched termination according to a characteristic impedance of the bus to which the module is connected and a matching resistor disposed between the bus and the module. The matching resistor has a resistance value Rm represented as

Information processing apparatus and backboard having on backboard side

Growing community of inventors

Yokohama, Japan

Yukihiro Seki