Renesas Electronics Corporation

Kowa Company Limited

Fujitsu Corporation

Renesas Technology Corp.

Konami Digital Entertainment Co., Ltd.

Pioneer Corporation

Mitsubishi Kasei Corporation

Fujitsu Microelectronics Limited

Yukihiro Sato

Tomoaki Uno

Katsuhiko Funatsu

Hiroyuki Nakamura

Kimiyuki Shibuya

Nobuya Koike

Toshiyuki Edano

Katsumi Kawamine

Takamitsu Kanazawa

Akira Muto

Kisho Ashida

Mitsuteru Hirata

Chiyoka Ozaki

Toru Miura

Tadaaki Ohgiya

Atsushi Fujiki

Tatsuhiro Seki

Nobuyoshi Matsuura

Tetsuya Kawashima

Hiroyoshi Taya

Keiichi Okawa

Norio Kido

Masahiro Koido

Takahiro Kitamura

Koji Bando

Kazuhiro Mitamura

Yuichi Yato

Toru Ueguri

Ichio Shimizu

Masami Shiratsuchi

Atsushi Nishikizawa

Ryo Kanda

Toshinori Kiyohara

Katsuo Ishizaka

Souhei Tanabe

Masaru Nakamura

Kenji Kobayashi

Ryotaro Kudo

Nobuyuki Shirai

Eiichi Hoshino

Kazunori Hasegawa

Kenya Kawano

Hitoshi Yamasaki

Masato Miyazaki

Hiroya Shimoyama

Koji Hosono

Toshikatsu Minagawa

Yasuo Kamoshita

Heihachi Yushina

Hirofumi Oda

Kazumasa Sugawara

Yukizumi Terao

Nobuhiro Mochizuki

Katsutoshi Yoshida

Yuuichi Yamamoto

Masahiko Uraguchi

Hirotatsu Hiruta

Provided is a terminal device and the like that can switch a mode of operation as a terminal device in relation to an on-board device to which the terminal device is attached. A terminal device T that is attached to an attachment target device M and that communicates with the attachment target device M comprises a switching meansthat switches a mode of operation of the terminal device T on the basis of a state of attachment to the attachment target device M and a state of communication with the attachment target device M.

Terminal device, information processing method, and program for terminal device

A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

Semiconductor device

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Semiconductor device and method of manufacturing the same

Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

Semiconductor device with metal patterns having convex and concave sides

On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

Semiconductor device and manufacturing method thereof

To improve the reliability of a semiconductor device. A chip mounting portion TABis arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP(LV) and a pad of a semiconductor chip CHPare electrically coupled by a wire Wand a wire Wthrough a relay lead RL. Likewise, a gate electrode pad of a semiconductor chip CHP(LW) and the pad of the semiconductor chip CHPare electrically coupled by a wire Wand a wire Wthrough a relay lead RL. At this time, the structures of parts of the relay leads RLand RL, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LDand LDwhich function as external terminals.

To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Method of manufacturing semiconductor device

Power module with a plurality of patterns with convex and concave side

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS&#x2022;FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die padD, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Semiconductor device having a chip mounting portion on which a separated plated layer is disposed

Growing community of inventors

Tokyo, Japan

Yukihiro Sato