Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Yukihiro Sasagawa

Shiro Dosho

Masaya Sumita

Shiro Sakiyama

Taketo Heishi

Takashi Morie

Hajime Ogawa

Minoru Okamoto

Yusuke Tokunaga

Akinori Matsumoto

Naoki Nojiri

Takenobu Tani

Ryutaro Yamanaka

Ryuta Nakanishi

Kazuaki Sogawa

Kazuhiro Okabayashi

Atsushi Takahata

Tetsuya Tanaka

Tatsuya Tetsukawa

Chua Tien Ping

Michael Bi Mi

A map information update method includes: (a) obtaining map information; (b) obtaining landmark observed positions indicating positions of one or more landmarks in a captured image; (c) adding that includes (i) generating added map information by adding information pertaining to the landmark observed positions to the map information, and (ii) updating the map information obtained in (a) to the added map information; (d) predicting that includes (i) calculating predicted map information based on the map information updated in (c), by using a neural network inference engine that has been trained, and (ii) updating the map information to the predicted map information; and updating information that includes (i) calculating updated map information based on the map information updated in (d), by using a gradient method, and (ii) updating the map information to the updated map information.

Map information update method, landmark generation method, and feature point distribution adjustment method

A color image inpainting method includes: obtaining a color image of an object to be recognized, the color image including a missing portion where at least part of image information is missing; obtaining an infrared image of the object; identifying the missing portion in the color image; and inpainting the missing portion in the color image identified in the identifying. The inpainting includes inpainting the missing portion by using information which is obtained from the infrared image and corresponds to the missing portion to obtain an inpainted color image of the object.

Method for complementing color image using machine-learning model

A quantization parameter optimization method includes: determining a cost function in which a regularization term is added to an error function, the regularization term being a function of a quantization error that is an error between a weight parameter of a neural network and a quantization parameter that is a quantized weight parameter; updating the quantization parameter by use of the cost function; and determining, as an optimized quantization parameter of a quantization neural network, the quantization parameter with which a function value derived from the cost function satisfies a predetermined condition, the optimized quantization parameter being obtained as a result of repeating the updating, the quantization neural network being the neural network, the weight parameter of which has been quantized, wherein the function value derived from the regularization term and an inference accuracy of the quantization neural network are negatively correlated.

Quantization parameter optimization method and quantization parameter optimization device

An image recognition system for detecting and tracking at least an image portion associated with a predefined object from a moving picture is configured to be able to perform: an object detection processing step of detecting the object; a tracking point specification processing step of specifying a predetermined point as a tracking point; a tracking target recognition processing step of recognizing an actual tracking target based on the tracking point; a tracking processing step of tracking the tracking target; and a determination processing step of determining the type of the tracking target's behavior. The tracking point specification processing step and the determination processing step are implemented by software, while the object detection processing step, the tracking target recognition processing step, and the tracking processing step are implemented by hardware.

Image recognition system and semiconductor integrated circuit

A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Panel control device and panel control system

A neural network system that can minimize circuit resources for constituting a self-learning mechanism and be reconfigured into network configurations suitable for various purposes includes a neural network engine that operates in a first and a second operation mode and performs an operation representing a characteristic determined by setting network configuration information and weight information with respect to the network configuration, and a von Neumann-type microprocessor that is connected to the neural network engine and performs a cooperative operation in accordance with the first or the second operation mode together with the neural network engine. The von Neumann-type microprocessor recalculates the weight information or remakes the configuration information as a cooperative operation according to the first operation mode, and sets or updates the configuration information or the weight information set in the neural network engine, as a cooperative operation according to the second operation mode.

Neural network system

A data compressing method comprises first step in which a data is orthogonally transformed so that an orthogonal transform data is generated. A processing step executed subsequent to the first step is divided into a processing step for an alternate-current component of the orthogonal transform data and a processing step for a direct-current component of the orthogonal transform data. The processing step for the direct-current component includes a second step in which an inverse transform equivalent to a decoding process of the orthogonal transform data is executed on the orthogonal transform data.

Signal processor

A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Pulse synthesis circuit

A semiconductor integrated circuit system has a control target circuit executing a program, a system information monitor unit for outputting system information indicating a state of the control target circuit, a circuit characteristic monitor unit for determining a circuit characteristic of the control target circuit and outputting the circuit characteristic as circuit characteristic information, a malfunction determination unit for determining whether or not the control target circuit is normally operating based on the system information, a reference circuit characteristic holding unit for holding the circuit characteristic information as reference circuit characteristic information when the control target circuit is normally operating, a malfunction factor determination unit for determining a malfunction factor based on the circuit characteristic information and on the reference circuit characteristic information when the control target circuit is not normally operating, and a correction target determination unit for determining a correction target in the control target circuit.

Semiconductor integrated circuit system, semiconductor integrated circuit, operating system, and control method for semiconductor integrated circuit

The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

Dynamic circuit

An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (), and one or more second instruction sets including control specification information (). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Low power operation control unit and program optimizing method

A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions

A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plurality of evaluation elements for evaluating data received at a first stage from the signal source to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements evaluates the data input to the evaluation element.

Event-driven logic circuit

A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a program synchronization flag of a program controller. A master processor, responsible for program control of the entire system, notifies an instruction memory section for storing instructions in a program of updated information when the program synchronization flag information is updated.

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Kyoto, Japan

Yukihiro Sasagawa