Sony Corporation

Yukihiro Sakamoto

Yoshihito Ishibashi

Teppei Yokota

Nobuyuki Kihara

Takumi Okaue

Asami Mizuno

Masaru Goto

Hiroaki Miyachi

Andrew Leung

An object detection control apparatus includes: a detection processing allocating unit that allocates object detection processing to any one of plural object detecting units that perform the detection processing on the basis of a transfer image area; a size generating unit that generates size of the transfer image area according to a detection area for the object detecting-unit to which the detection processing is allocated; and a reference-position generating unit that generates a position serving as a reference for the transfer image area using the generated size of the transfer image area and a position serving as a reference for the detection area moved by a predetermined number of pixels at a time.

Object detection control apparatus, object detecting system, object detection control method, and computer program

A security unit to prevent unauthorized retrieval of data includes an encrypting unit for encrypting data in accordance with commands received by the security unit, and a common register for storing both intermediate results and final results of the data encryption. A switching element operatively coupled to the register selectively outputs the contents of the register. The switching element is controlled to prevent external access to the intermediate results of the encryption. The security unit is particularly useful as part of a memory unit that is attachable to a recording/reproduction device such as a digital audio recorder/player.

Security unit for use in memory card

A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.

Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions

Growing community of inventors

Kanagawa, Japan

Yukihiro Sakamoto