Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokai University Educational System

Pilkington Micro-electronics Limited

Yukihiro Saeki

Yasoji Suzuki

Tomohisa Shigematsu

Osamu Matsumoto

Toshimasa Nakamura

Tetsuya Yamamoto

Hiroaki Suzuki

Masayuki Yoshida

Akira Takiba

Fuminari Tanaka

Kenneth Austin

Kazuyuki Uchida

Gordon S Work

Hiroki Muroga

Teruo Uemura

Kenji Toyoda

Nobuyoshi Chida

Hitoshi Kondo

Takahide Mizutani

Yasuo Kawahara

Hiroyuki Takamura

Kazunao Maru

Toshio Hibi

Darren M Wedgwood

Shinichi Osera

According to the present invention, there is provided an operation mode setting circuit comprising:

Operation mode setting circuit

A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.

Voltage transfer circuit and a booster circuit, and an IC card

A clock signal generated by a clock signal generating circuit is supplied to a frequency-dividing circuit formed using a D-type flip-flop circuit, being supplied to a controlled circuit after being divided down. Furthermore, the clock signal generated by the clock signal generating circuit is supplied to the controlled circuit by way of a through circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity of the frequency-dividing circuit, the through circuit being formed using the D-type flip-flop circuit in the same way as the frequency-dividing circuit.

Clock signal supplying circuit

A first test circuit is connected to one end of a first wiring line, and a second test circuit is connected to one end of a second wiring line. The second wiring line serves as a data bus. N-channel MOS transistors, connected in series, are provided between the first and second wiring lines and located below a third wiring line. The transistors are set in a conductive state by a gate control signal from a test control circuit in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines is small and does not adversely affect the operation speed of an integrated circuit.

Semiconductor integrated circuit including test circuit

A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.

Configurable logic element with independently clocked outputs and node

An EPROM integrated circuit includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit, a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to select a bank, a write number storage area is provided in the EPROM integrated circuit, and the contents of the write number storage area are updated by a write number updating circuit each time the write operation is performed for a new bank.

Nonvolatile semiconductor memory system

A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.

Manufacturing method for a floating gate semiconductor memory device by

A programmable logic device comprises a data storage circuit for storing 1-bit control data and a MOS transistor which is switch controlled in accordance with stored data in the data storage circuit. When the MOS transistor is switch controlled, the power supply voltage of the data storage circuit is raised. Two signal lines are connected with each other through the MOS transistor which has been rendered conductive, thereby permitting a signal to be transmitted between the signal lines.

Programmable logic device and storage circuit used therewith

A potential detecting circuit comprises a first MOS transistor of a first conductivity type whose drain receives an input potential that is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor of the first conductivity type whose source is connected to the second MOS transistor, source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.

Potential detecting circuit

A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

Semiconductor memory having load transistor circuit

A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate for deriving a logic output of two signals. The 2-input logic gate is constituted by connecting two 3-state circuits in a wired OR configuration. One of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal of the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Likewise, the other 3-state circuit includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Each of the data input terminals of the 3-state circuits is supplied with a desired one of the first signal, an inverted signal of the first signal, a '0' level signal, and a '1' level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.

Programmable logic circuit using wired-or tristate gates

Semiconductor memory with p-channel load transistor

An opening is formed at a position substantially midway along the widthwise direction of a wide metal wiring layer formed on a semiconductor substrate. A second metal wiring layer is formed in the opening in the same step for forming the wide first metal wiring layer. Drain electrodes of a CMOS inverter formed below the wide first metal wiring layer are connected to the second metal wiring layer through contact holes. The second metal wiring layer is connected to a polycrystalline silicon layer as an output wiring layer through a contact hole.

MOS semiconductor device having a low input resistance and a small drain

A bus line drive circuit comprising a bus line allowing data to transfer therethrough, a precharge circuit connected to the bus line for precharging the bus line with precharge pulse, input/output circuit connected to the bus line for transferring data to and from an ALU through the bus line, and positive feedback circuit connected to the bus line, which exhibits a high impedance during a precharge period to electrically be disconnected from the bus line, keeps a precharge potential when the potential on the bus line is equal to the precharge potential during an active period, and expands a potential difference when the potential on the bus line is slightly different from the precharge potential.

Bus line drive circuit

A sense amplifier circuit is disclosed in which a ROM is grouped into a plurality of ROM arrays and outputs from sense amplifiers provided for each ROM array are supplied to a single output terminal. In the sense amplifier circuit, each sense amplifier has a P-MOS FET connected between the output of the ROM array and a ground terminal and connected at the gate to a preset terminal, P-MOS FETs connected between the output of the ROM array and a positive power source and whose gates are respectively connected to the output terminal and a preset terminal, and an N MOS FET connected between the output terminal and the ground terminal and at the gate to the output terminal of the ROM array. Further, a P MOS FET is connected between the output terminal and the power source terminal and at the gate to an inverted preset terminal.

Growing community of inventors

Yokohama, Japan

Yukihiro Saeki