Fujitsu Corporation

Fujitsu Vlsi Limited

Yukihiro Nomura

Yoshihiro Takemae

Takaaki Furuyama

Mitsuhiro Nagao

Masahiro Niimi

Yasuharu Satoh

Hiroyoshi Tomita

Shinichi Yamada

Yasurou Matsuzaki

Koichi Nishimura

Hirohiko Mochizuki

Tatsuya Kanda

Shigemasa Ito

Hiroyuki Fujimoto

Takahiro Suzuki

Eiichi Nagai

Masahiko Saitou

A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

Semiconductor memory and system apparatus

The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

Self-test circuit and memory device incorporating it

A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

DRAM with reduced electric power consumption

A data transfer apparatus is disclosed which has a first, a second, and a third pipeline processing circuits disposed in cascade connection. The first and the second pipeline processing circuits are each provided with an arbitrary signal processing circuit, a switch element for controlling the introduction of data into the signal processing circuit, and a switch control circuit for turning on the switch element on detecting completion of the transfer of data from the signal processing circuit to a pipeline processing circuit in the subsequent stage. The third pipeline processing circuit is provided with an output circuit and a switch element for introducing data transferred from the second pipeline processing circuit into the output circuit as synchronized with an external clock signal. Between the first and the second pipeline processing circuit, therefore, data can be transferred with a timing conforming to the timing of the operation of the signal processing circuit without being synchronized with an external clock signal. In the output circuit, data can be issued as synchronized with an external clock signal. Thus, a signal of a very high frequency can be selected as a clock signal for setting the timing of the whole of a system incorporating the data transfer apparatus therein.

Apparatus for data transfer capable of pipeline processing by cascading

An LSI device can provide a desired constant value of a step-down voltage even if there are variations due to the production processes and a stable characteristic of internal circuits is obtained. The LSI device such as a DRAM includes a first input terminal of the high-voltage-side external supply voltage, a constant current source and a second input terminal of the low-voltage-side supply voltage. Further, the device includes a circuit which makes a voltage between two terminals variable due to the disconnection of each fuse. A step-down circuit is formed by the constant current source and the load circuit and provides a step-down voltage V.sub.B for stepping down the external supply voltage V.sub.CC.

Semiconductor integrated circuit device having built-in step-down

A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Growing community of inventors

Kawasaki, Japan

Yukihiro Nomura