Kabushiki Kaisha Toshiba

Yukihiro Nishida

Kiyoharu Oikawa

Masaya Kubota

Takeshi Dairiki

Junji Morita

An oscillation apparatus includes: an oscillation circuit; a timing control circuit that generates a timing signal using an output clock of the oscillation circuit; an integration circuit that cyclically integrates a reference current based on the timing signal to output an output voltage value; a comparison circuit that compares the output voltage value of the integration circuit with predetermined threshold voltage and outputs a comparison result; a steady voltage changing circuit that, when it is shown by the comparison result of the comparison circuit that the output voltage value of the integration circuit exceeds the threshold voltage, returns the output voltage value of the integration circuit by a predetermined amount; and a frequency adjustment circuit that generates a control signal for adjusting an oscillation frequency of the oscillation circuit based on a value obtained by averaging the comparison result in plurality of the comparison circuit.

Oscillation apparatus and oscillation frequency adjustment method

A plurality of dummy cells which generate reference potential corresponding to a capacitance of a bit line each have a floating gate, control gate and first and second diffusion layers. The first and second diffusion layers of each dummy cell are commonly connected by use of a wiring.

Nonvolatile semiconductor memory device containing reference capacitor circuit

A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.

Memory circuit apparatus

A quasi-composite video signal generator incorporated in a microcomputer having a circuit for generating a quasi-composite video signal to be used to adjust a cathode ray tube (CRT) of a display unit, and the microcomputer being incorporated in the display unit. This generation circuit has a synchronous signal generation section for generating horizontal and vertical synchronous signals, a display setting unit for setting an image to be displayed, and a signal generator for generating a three-state signal Vout according to the image set by the display setting unit and the horizontal and vertical synchronous signals. The signal Vout is converted by a shaping circuit into the quasi-composite video signal, which is applied to drivers of cathode electrodes of the CRT.

Growing community of inventors

Yokohama, Japan

Yukihiro Nishida