Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yukihiro Nagai

Tomoharu Mametani

Hiroaki Nishimura

Takeshi Kishida

Akinori Kinugasa

Jiro Matsufusa

Shigenori Kido

Yoji Nakata

In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Semiconductor device having a potential fuse, and method of manufacturing the same

A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Semiconductor device having test mark

There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Semiconductor device, and method of manufacturing the same

A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.

Semiconductor device and manufacturing method thereof

A method of manufacturing semiconductor device is provided which can minimize the thinning of a nitride layer in the planarization process and inhibit the peripheral area of the nitride layer from being excessively polished. The method of manufacturing semiconductor device includes the steps of: forming a nitride layer on a semiconductor substrate; patterning the nitride layer and etching the semiconductor substrate while masking with a pattern of the nitride layer to form a trench; depositing an oxide layer to fill the trench and cover the nitride layer; patterning a resist layer on the oxide layer; etching the oxide layer on the nitride layer; and planarizing the oxide layer, wherein the step of etching the oxide layer permits a thickness of the oxide layer to be left on the nitride layer.

Method of manufacturing a semiconductor device

A magnetic random access memory or the like has a plurality of magnetic storage elements laminated on a single transistor, resulting in a reduction in the number of necessary components and a considerable enhancement in the degree of integration of the memory. A magnetic random access memory or the like, comprises a plurality of magnetic storage elements for magnetically storing information, a plurality of bit lines, each of which connected to each of the plurality of magnetic storage elements, a plurality of writing word lines, each of which is provided in correspondence to the vicinity of each of the plurality of magnetic storage elements and utilized for applying magnetic field to write the information, a single reading word line, and a switch including a first terminal and a second terminal, the first terminal being connected to the single reading word line to be utilized for determining whether current is caused to flow to the second terminal, the second terminal being connected to each of the plurality of magnetic storage elements.

Magnetic random access memory

A semiconductor device includes a semiconductor substrate, a lower interlayer film formed on an upper side thereof, an intermediate film formed on an upper side thereof, an upper interlayer film formed on an upper side thereof, and a lower plug made of an electrically conductive material that penetrates through the lower interlayer film and the intermediate film. However, the intermediate film has such a material quality that a ratio of an etching rate of the intermediate film to an etching rate of the upper interlayer film is sufficiently small to allow processing of the upper contact hole by etching the upper interlayer film using the intermediate film as a stopper under an etching condition for forming the upper contact hole.

Semiconductor device and production method thereof

A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film ( ) formed of p-TEOS is deposited to cover a substrate ( ) and wires ( ) formed on the substrate ( ). A second insulation film ( ) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate ( ); therefore, the second insulation film ( ) is etched. The etching is stopped at the point where the surface ( ) of the first insulation film ( ) on the wires ( ) is exposed. This ensures good surface,planarity. A third insulation film ( ) is stacked on top of the second insulation film ( ), and portions of the third insulation film ( ) above the wires ( ) are isotropically etched to form openings ( ). At this time, the isotropic etching does not extend over the second insulation film ( ).

Method of manufacturing contact structure

Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (,) in which impurity is diffused is deposited on the entire surface including the inside of a hole (,A). An etching process of the polysilicon layer (,) is performed to form a storage node electrode composed of the polysilicon layer (,) remaining on the bottom and side of a groove for metallization (,) and in the hole (,A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (,), and a plug part disposed in the hole (,A). The storage node electrode is electrically connected via the plug part to a diffused region (,) of a semiconductor substrate (,).

Method of manufacturing semiconductor device

There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.

An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower conducting layer is formed on a second interlayer insulating film. A third interlayer insulating film covers lower conducting layer. A contact hole is formed in third interlayer insulating film in order to connect an upper conducting layer and lower conducting layer. A stopper layer of silicide or metal is formed below contact hole between the surface of a semiconductor substrate and lower conducting layer.

Semiconductor device with improved interconnection

Obtaining a semiconductor device which can reduce the occupied area of a capacitor in a logic circuit area while ensuring a constant capacitance without increasing the number of steps of fabricating the semiconductor device, and a method of fabricating the same. A first electrode of a capacitor is formed in the logic circuit area. A dielectric film consisting of a first interlayer isolation film is formed on the first electrode. A second electrode is formed on the first interlayer isolation film. A second dielectric film consisting of a second interlayer isolation film is formed on the second electrode. A third electrode is formed on the second interlayer isolation film. A connecting wire connects the first electrode and the third electrode with each other through openings in the first and third connecting regions.

Semiconductor device comprising capacitor in logic circuit area and

On a semiconductor substrate, a first circuit and a second circuit are provided with a space therebetween. The first circuit and the second circuit are connected to each other by a fuse portion. In the middle of the fuse portion, a connecting portion is interposed, which is made of a material highly resistant to corrosion. Accordingly, an improved semiconductor device with a corrosion-resisting fuse portion is accomplished, which ensures the layout to be designed much more freely.

Growing community of inventors

Tokyo, Japan

Yukihiro Nagai