Kitakyushu Foundation for the Advancement of Industry, Science and Technology

Yukihiro Iguchi

Tsutomu Sasao

A device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions. The device includes means to store node tablestoring Binary Decision Diagram for Characteristic Function (BDD_for_CF) of the characteristic function &#x3c7;(X, Y) of the multiple-output logic function f(X), means to store LUTs, means to reduce by shortingpartitioning BDD_for_CF into the subgraphs Band Bat the partition line in the height lev of the partition and executing shorten-processing, means to measure the width W of BDDscalculating the width W at the partition line, means to compute the intermediate variablescalculating the number of the intermediate variables u according to the width W, means to generate an LUTgenerating the LUT for the sub-graph B, and means to reconstruct BDDsgenerating a binary tree that has the same number of control inputs as that of the intermediate variables u, replacing the sub-graph Bwith the binary tree and reconstructing the BDD_for_CF.

Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis

The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic () are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (). The interconnection circuit () connects the output lines or the external input lines of memory for logic () in the preceding stage and the input lines of memory for logic () of the succeeding stage between two memories for logic (), according to the information for connection memorized in memory for interconnections (). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed. The size of memory can be suppressed to the minimum by optimizing the ratio of the number of rail and the number of input lines according to the logic function.

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Kanagawa, Japan

Yukihiro Iguchi