Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Yukihiro Fukumoto

Takeshi Nakayama

Yoshiyuki Saito

Hiroshi Ikeda

Shinichi Tanimoto

Osamu Shibata

Eiji Takahashi

Yutaka Nakamura

Yoshihiro Bessho

Yutaka Taguchi

Hideki Iwaki

Hiroshi Suenaga

Satoshi Hasako

Tetsuyosi Ogura

Hiroshi Benno

Hirokazu Uemura

A high-speed interface connector is used for connecting a cable or a memory card each having a differential transmission system signal pin arrangement including a pair of differential transmission signaling pins that are adjacent to each other and two stable potential pins provided on both sides of the pair of differential transmission signaling pins, the two stable potential pins having potentials different from each other. The connector includes: a first and a second contact terminals for differential transmission respectively connected to the pair of differential transmission signaling pins; and a third and a fourth contact terminals provided on both sides of the first and the second contact terminal, the third contact terminal adjacent to the first contact terminal being connected to one of the two stable potential pins, and the fourth contact terminal adjacent to the second contact terminal having a potential identical to that of the third contact terminal.

High-speed interface connector

A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device

A CAD apparatus includes a determining unit for determining a component order in ascending order of impedance of components for passive components amongst components to be placed on a printed wiring board. The CAD apparatus places each passive component in the determined component order in a vicinity of power pins of non-passive components that are already placed.

Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise

The power line carrier system provides with a filter in a power branch apparatus removable from an external power line. The filter passes a power line carrier signal in a signal mode for the external power line, and interrupts another power line carrier signal which is in a signal mode different from the mode for the external power line.

Power line carrier system

A signal line, being in a six-layer board and connecting terminalof componentwith terminalof componentrequires tamper-resistance. The signal line is composed of foilon an outside layer, a viafoilon the third layer, viafoilon the fourth layer, viaand foilon the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foiland an end of viaare placed under componenton first layeran end of viais placed under componenton layeran end of viais placed under componenton layerthe other end of viais placed under componenton sixth layerthe other end of viais placed under componenton layerand foiland the other end of viaare placed under componenton layer

MULTILAYER BOARD IN WHICH WIRING OF SIGNAL LINE THAT REQUIRES TAMPER-RESISTANCE IS COVERED BY COMPONENT OR FOIL, DESIGN APPARATUS, METHOD, AND PROGRAM FOR THE MULTILAYER BOARD, AND MEDIUM RECORDING THE PROGRAM

A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.

Bidirectional signal transmission circuit and bus system

A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.

Circuit board design aiding

The semiconductor package of this invention includes: a semiconductor element having a power supply terminal, a ground terminal, and an output terminal; an inductance; and a capacitance. One of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element, and the other terminal is connected to the ground terminal of the semiconductor element. The ground terminal of the semiconductor element is connected to a ground terminal of the semiconductor package, the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package via the inductance, and the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.

Growing community of inventors

Hirakata, Japan

Yukihiro Fukumoto