Kabushiki Kaisha Toshiba

Matsushita Electric Industrial Co., Ltd.

Yukihiro Fujimoto

Kazutaka Nogami

Takeshi Sugahara

Seiro Imai

Hidetoshi Suzuki

Yukihiro Urakawa

Takaaki Nakazato

Toshihiro Ishikawa

Tomohiro Kobayashi

Fujio Ishihara

Tsuguo Kobayashi

Noriaki Minamida

A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on the data path circuits and control circuits. Each of data path circuits includes a memory cells disposed in rows along the first direction and columns along a second direction crossing the first direction and a read/write circuit disposed at an end of the columns of memory cells. At least one pair of adjacent columns of memory cells has an electrical separation between the gate polysilicon layer the pair of adjacent memory cell columns&#x2014;that is, gate conductor layer of the adjacent memory columns are electrically distinct. A word line in the first metal layer is segmented along the first direction into separately addressable portions.

Semiconductor memory device

A semiconductor integrated circuit includes a first region configured to operate at a specified first voltage, a second region configured to operate at a varying second voltage, and a memory device formed between the first region and the second region so as to straddle the first and second regions, wherein the memory device comprises a first port driven at the first voltage to transmit an output signal to and receive an input signal from the first region, a second port driven at the second voltage to transmit an output signal to and receive an input signal from the second region, and a memory cell accessed by the first and second ports.

Semiconductor integrated circuit

A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a pair of storage nodes that are complementary to each other. One storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a global bit-line. The other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a local bit-line. The global bit-line is a bit-line connected in common to the plurality of the sub arrays. The local bit-line is provided for each of the sub arrays.

LSI deviceis provided with standard cell regions, a plurality of standard cells, memory blocksand a plurality of memory cells. Standard cellsare equal in height 'Hs' and disposed in standard cell regionsin a vertical direction. Memory blocksare provided in contact with standard cell regionin a horizontal direction and memory cellsare disposed in memory blocksin the vertical direction. Height 'Hm' of memory cellsis equal to the height &#x201c;Hs&#x201d; or the height of the standard cell divided by an integer. Boundary positions of standard cellsneighboring each other are consistent with those of memory cellsneighboring each other.

Semiconductor integrated circuit device

A semiconductor memory includes memory cells for even addresses arranged in a first memory array and storing even addressed data, word lines for even addresses arranged parallel to a row direction of the first memory array and selecting the memory cells for even addresses, bit lines for even addresses arranged parallel to a column direction of the first memory array and transferring the even addressed data to the memory cells for even addresses, memory cells for odd addresses arranged in a second memory array and storing odd addressed data, word lines for odd addresses arranged parallel to a row direction of the second memory array and selecting the memory cells for odd addresses, and bit lines for odd addresses arranged parallel to a column direction of the second memory array and transferring the odd addressed data to the memory cells for odd addresses.

Semiconductor memory

A semiconductor memory device is disclosed, which includes a first SRAM cell which includes cross-connected first and second inverters having first and second nodes, a first transistor connected between a first bit line and the first node and having a gate connected to a first write word line, a second transistor connected between a second bit line and the second node and having a gate connected to the first write word line, a third transistor having a gate connected to the second node, a fourth transistor connected between the first bit line and the third transistor and having a gate connected to a read word line, and a second SRAM cell which includes fifth-eighth transistors corresponding to the first-fourth transistors and has substantially the same configuration as the first SRAM, wherein the drains of the fourth and eighth transistors are connected to the first and second bit lines, respectively.

A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.

A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.

Semiconductor memory device having hierarchical bit line structure

A plurality of sub-arrays include a plurality of memory elements. First bit line pairs are connected to a plurality of memory elements provided in each of the sub-arrays. Second bit line pairs are provided so as to correspond to a plurality of sub-arrays. The first bit line pairs supply signals to the second bit line pairs. The second bit line pairs are operated at a lower frequency than the first bit line pairs.

Semiconductor memory device capable of operating at high speed

A content addressable memory which detects whether p (where p is an integer of 2 or more) bit sequences coincide respectively with reference bit sequences, said content addressable memory comprising: q comparison units which compares bit groups obtained by dividing the p bit sequences into q (where q is an integer of 2 or more) parts with corresponding bit groups in the reference bit sequences in p times; a precharge unit which precharges output lines of said q comparison units; and a comparison control unit responsive to a decision of noncoincidence in at least one of said q comparison units while said q comparison units are conducting an r(where r is an integer variable that is 1 or more and that is at most p&#x2212;1, and p is an integer of 2 or more) comparison operation, which stops precharging to be performed by said precharge unit at time of an (r+1)comparison operation and subsequent comparison operations.

Content addressable memory and memory system

A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by the word lines, a leak detecting line, leak generators configured to provide the leak detecting line with a leakage current and a signal compensator configured to detect a voltage state of the leak detecting line and to change the signals transmitted by the bit lines.

Leak immune semiconductor memory

A semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first and a second direction; a plurality of local bit lines in the sub-memory arrays; a plurality of word lines in the sub-memory arrays; a plurality of global bit lines connected the local bit lines via switching circuits; a plurality of read/write circuits connected to the global bit lines; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array, and a second sub-memory cell array; and an address decoding circuit decoding the first and second address signals, and activating a first word line connected to a memory cell of the first sub-memory cell array and a second word line connected to another memory cell of the second sub-memory cell array.

Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device

A memory operating method includes selecting memory cells on a word line; transmitting potential levels of memory cells selected by the word line; pre-charging bit lines; amplifying the potential levels of the memory cells selected by the word line which are read to the bit lines; pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; driving the bus line on the basis of a gate control signal; and transmitting the gate control signal so as not to drive the bus line when an enable signal is in an inactive state, and transmitting the gate control signal so as to drive the bus line on the basis of the potential of the bus line and output data of the amplifying means when the enable signal is in an active state.

Bus driving circuit and memory device having same

A semiconductor device comprises a first bit line, a second bit line, a memory cell electrically coupled to the first bit line and the second bit line, a first amplification circuit configured to amplify a potential of the first bit line and a second amplification circuit configured to amplify a potential of the second bit line.

Growing community of inventors

Yokohama, Japan

Yukihiro Fujimoto