Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yukihiko Shimazu

Toyohiko Yoshida

Narumi Sakashita

Toshiki Fujiyama

Hiroyuki Kobayashi

Hiromi Maeda

Katsunori Sawai

Toshio Kishi

Taketora Shiraishi

Ikuo Yasui

Kohji Kawamoto

Katsumi Dosaka

Masaki Kumanoya

Toru Shimizu

Genichi Tanaka

Masayuki Hata

Akira Oizumi

Toshiki Kanamoto

Souichi Kobayashi

Toru Kengaku

Eiichi Teraoka

Yukari Takata

Norio Masui

Yasufumi Mori

Yoshihide Ajioka

Kazuyuki Ishikawa

Nubuhiko Honda

Teruyuki Itou

Soichi Kobayashi

Hideyuki Hamada

Nobuhiko Honda

Hisako Mizuoka

Akihiko Ishida

Nobuhiko Honoa

Yoshiaki Yamazaki

Nobuniko Honoa

In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to '0' when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to '1' when once the comparison result for the corresponding column indicates difference.

Semiconductor integrated circuit capable of testing with small scale circuit configuration

A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number information indicative of the number of wait cycles for an access by the CPU to that peripheral circuit, and a wait control circuit providing wait control for the access by the CPU to that peripheral circuit based on the number of wait cycles held by the wait control register.

Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU

A bus control circuit includes cycle registers provided with areas for holding signal levels of system-to-external bus control signals such that each of the cycle registers is provided for a corresponding cycle. A default register, additionally included in the bus control circuit, holds signal levels of the system-to-external bus control signals in a normal state. The signal levels of the system-to-external bus control signals held in the corresponding areas in the cycle registers are output cycle by cycle. When the normal state takes over, the signal levels held in the corresponding areas in the default register are output.

Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level

A data processing unit includes a first power supply consisting of a stable power supply, a central unit operating on the firsts power supply, a second power supply, a peripheral unit operating on the second power supply, an interface block for transferring an external signal to the peripheral unit, and a power-down detector operating on the first power supply and connected to the second power supply, for detecting a power down of the second power supply and for generating a signal informing of the power down when it occurs. This power down signal can prevent supply of the external input signal to the central unit. The data processing unit solves problems of conventional data processing units including separate central unit and peripheral power supplies in that an unexpected power down of the peripheral use power supply can cause malfunctions of the central unit because of, e.g., an undesired interrupt signal.

Data processing unit including central unit and peripheral unit driven by separate power supplies

In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input terminal of the standard cell and gates of the MOS transistors are connected through the diffused region. Also, a diffused region is formed under the input terminal in the substrate, and the input terminal is connected to the diffused region. In a modification, another standard cell is formed by forming a diffused region and a metal layer connected to the diffused region on the substrate, and the another standard cell is connected to the input terminal.

Semiconductor device having a library of standard cells and method of designing the same

An auto placement and routing device lays out wiring with consideration for influences of an increase in an effective coupling capacitance. A layout data generation unit allots signal lines ( to ) to grids ( ), respectively. The signal lines ( ) have a signal attribute B, and the signal lines ( ) have a signal attribute A. Thus, the signal line having the signal attribute A and the signal line having the signal attribute B are placed by turns so that the signal lines having the same signal attribute are not to be adjacent to each other. Accordingly, the potential transitions of the signal lines ( ) adjacent to an observed signal line ( ) do not take place at a time when the potential transition of the observed signal line ( ) takes place. This prevents an increase in the effective coupling capacitance of the observed signal line ( ) due to the potential transitions of the signal lines ( ) adjacent to the observed signal line ( ).

Auto placement and routing device and semiconductor integrated circuit

A data processor is provided to increase the number of instructions it can handle, even with a large number of operands required for the instructions. The data processor comprises a decoding circuit ( ) extracting bits (a , a ) of an instruction as first operand fields and decoding an operation code, using the remaining bits (a4); an operand-field storage portion ( ) including a first operand-field storage portion ( a) storing bits (a , a ) obtained from the decoding circuit ( ) via a selector ( ), and a second operand-field storage portion ( b) storing a second operand field obtained on the basis of those bits (a ); and a data processing portion ( ) receiving the first and the second operand fields from the operand-field storage portion ( ) and processing data in registers designated by the first and the second operand fields.

Data processor capable of handling an increased number of operation codes

There is provided an automatic placement and routing device which automatically performs placement and routing upon cells constituting a logic circuit while optimizing a bus structure. Bus structure construction means (,) constructs the bus structure which is a structure of signal lines for making connection between the cells to provide a bus construction result, based on bus information held in a bus information holding portion (,), cell placement information, constraint information from a constraint information holding portion (,) and logic circuit information from a logic circuit information holding portion (,), when the logic circuit information held in the logic circuit information holding portion (,) does not completely specify the bus structure.

Automatic placement and routing device

A processing apparatus comprises a register file having a rectangle-shaped contour and including a plurality of registers each of which is comprised of a plurality of register cells, a first operating unit located opposite to a first side of the rectangular contour of the register file, a second operating unit located opposite to a second side of the rectangular contour of the register file which is opposite to the first side, a third operating unit located opposite to a third side of the rectangular contour of the register file which is different from the first and second sides, a first data bus disposed for transferring data between the first operating unit and the register file, a second data bus disposed for transferring data between the second operating unit and the register file, and a third data bus disposed for transferring data between the third operating unit and the register file.

Processing apparatus having reduced bus lengths between operating units

A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300), and a second clock signal (S11) passes only through the selected delay element(s). That is, the second clock signal (S11) does not pass through the non-selected delay element(s), which reduces power consumption.

Digital delay circuit and digital PLL circuit with first and second

A MOS integrated circuit comprising a middle potential node to which a middle potential is to be supplied, a first operation circuit operating between a first potential and the middle potential, a second operation circuit operating between the middle potential and a second potential, and a node stabilization circuit for stabilizing the potential of the middle potential node.

MOS integrated circuit with low power consumption

A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from:

Clock generating circuit, PLL circuit, semiconductor device, and methods

A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.

Microcomputer

A microprocessor with a built-in instruction ROM is described. Arbitrary data is set in advance in a data register of the microprocessor. The arbitrary data is given to a program counter by a register indirect jump instruction. The microprocessor has a normal reset function and an additional reset function allowing reset from a predetermined address. The additional reset function is used when the logic level of a control signal input terminal is at a predetermined level when the reset signal to the reset terminal is cleared. The arbitrary data is transferred to the program counter by register indirect jump instruction and set in the program counter. The program is re-executed with this data as an instruction start address.

Microprocessor with reset execution from an arbitrary address

Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Growing community of inventors

Itami, Japan

Yukihiko Shimazu