Fujitsu Corporation

Yukihiko Kitano

Naozumi Aoki

Masatoshi Sugino

Kenro Nagato

A memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems concurrently execute an operating process, and more particularly a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit in the data processing unit, and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in a tag copying unit in the memory control device. Information regarding whether a block including a process request address exists in the buffer memory unit and whether the block is being processed currently are simultaneously obtained by retrieving only the tag copying unit. Thus, the address comparing unit can be omitted because no address comparison is needed. This structure reduces the amount of hardware and improves the port use efficiency, thus realizing the reduced system construction cost and improved processing speed.

Memory control method/device for maintaining cache consistency with

The storage control system reduces the system load on a main storage unit by staggering data transfer to minimize a busy condition on the main memory bus, while maintaining a block size sufficient to ensure a good hit rate in a buffer storage. To achieve such a reduction, the system transfers a variable quantity of data from the buffer storage to the main storage unit, wherein the quantity of data is predetermined based on a detected load on the main storage unit. When the detected load is reduced, another variable quantity of data may be transferred.

Growing community of inventors

Kawasaki, Japan

Yukihiko Kitano