Hitachi, Ltd.

Texas Instruments Corporation

Other

Hitachi Ulsi Engineering Corp.

Micron Technology Incorporated

Elpida Memory, Inc.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Hiachi, Ltd.

Yukihide Suzuki

Shunichi Sukegawa

Masaya Muranaka

Kiyoshi Nakai

Kanehide Kenmizaki

Makoto Morino

Tetsuya Kitame

Shinichi Miyatake

Hidekazu Egawa

Makoto Saeki

Isamu Fujii

Koichi Abe

Tsugio Takahashi

Takashi Inui

Hiroyuki Yoshida

Yoshiro Riho

Sadayuki Morita

Sadayuki Okuma

Minoru Someya

Shigeki Numaga

Chisa Makimura

Noriaki Sakamoto

Katura Abe

Yutaka Ito

Yoshinobu Nakagome

Kouji Arai

Hitoshi Tanaka

Masamichi Ishihara

Shoji Kubono

Masayuki Nakamura

Toshiyuki Sakuta

Sinichi Miyatake

Katsuo Komatsuzaki

Shoji Wada

Masahiro Ogata

Masayuki Hira

Ryo Hirano

Hiromi Matsuura

Yoshihisa Koyama

Hidetomo Aoyagi

Tadashi Tachibana

Masahiro Katayama

Nobuhiko Ohno

Eiji Yamasaki

Ken Saitoh

Yoritaka Saitoh

Takayuki Aisu

Seiichi Shundo

Noriaki Kubota

Hiroyuki Fujiwara

Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Compensating offsets in buffers and related systems, methods, and devices

A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

Semiconductor integrated circuit

In a semiconductor integrated circuit device, a command decoder is adapted to receive not only an external command but also an internal command. An ECC controller has a command generator and an address generator. When the command decoder decodes an external entry command, the command generator instructs encoding to an ECC-CODEC circuit and the address generator sequentially produces addresses which are supplied to a memory array. The ECC-CODEC circuit produces check bits for error detection/correction with reference to information data of the memory array. Upon completion of an encoding operation of writing the check bits into a predetermined region of the memory array, the ECC controller delivers an end signal to the command decoder as the internal command to make a super self-refresh control circuit start a super self-refresh operation.

DRAM with super self-refresh and error correction for extended period between refresh operations

A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Semiconductor device with plural unit regions in which one or more MOSFETs are formed

Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Semiconductor memory device and memory system

In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance

In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

Semiconductor integrated circuit device

A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

Semiconductor storage device

A word line leak check test for a semiconductor memory arranged as a matrix which includes word lines and y-selection lines. First, a RAS signal is enabled while a prescribed row address is input, and word line 22 is driven to the Vpp level. Then, when the CAS signal is enabled, the voltage source is disconnected from word line 22, and word line 22 floats. Two bits for the column address are disregarded, and the Y selection signal line 23 is decoded without those 2 bits. By this means, 4 y-selection signal lines 23 are simultaneously enabled. When this condition has been maintained for a prescribed time T, a delayed write operation is conducted, and then it is determined whether the data has been correctly stored in memory cell 24.

Method for testing word line leakage in a semiconductor memory device

A semiconductor integrated circuit is provided in which a differential amplifier circuit such as a sense amplifier is operated at high speed even if the operating voltage is reduced. To achieve this, a MOS transistor for supplying the operating voltage to a drive line on the high-potential side of a differential amplifier circuit is of N-channel type and the amplitude of a switching control signal for controlling this transistor is the potential of the step-up voltage produced by stepping up a supply voltage in level. The output voltage of an internal step-up circuit for achieving a word-line selection level is utilizable as the step-up voltage.

Semiconductor integrated circuit utilizing overdriven differential

Growing community of inventors

Akishima, Japan

Yukihide Suzuki