Hitachi, Ltd.

Hitachi Device Engineering Co., Ltd.

Hitachi Displays, Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Other

Hitachi Ulsi Systems Co., Ltd.

Japan Display Inc.

Yukihide Ode

Mitsuru Goto

Hiroshi Katayanagi

Koichi Kotera

Yoshiyuki Saitou

Hironobu Isami

Haruhisa Iida

Yasuhiro Tanaka

Hidenori Kikuchi

Haruhisa Okumura

Kentaro Agata

Kazunari Kurokawa

Akira Ogura

Takahiro Fujioka

Hiroshi Watanabe

Shinji Yasukawa

Hirobumi Koshi

Shigeru Itou

Shuuichirou Matsumoto

Kouichi Kotera

Youzou Nakayasu

Hidetoshi Kida

Kazunari Saitou

Gou Yamamoto

Mamoru Yamanaka

A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Liquid crystal display device with influences of offset voltages reduced

There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

Display apparatus

A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to a reference voltage; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region-coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a do voltage.

Level converter circuit and a liquid crystal display device employing the same

A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.

There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.

A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.

A display device which transmits display data to drive circuits which drive a display panel using low voltage differential signals have input circuits which are hardly influenced by noise. To transmit the low voltage differential signals under the same condition, low voltage differential signal lines are formed in a zigzag pattern so as to make the lengths of the lines equal. To reduce the influence generated by the overlapping of the zigzagged low voltage differential signal lines and the drive circuits, level shift circuits are provided to the input circuits so as to make the input signals assume a stable operation level.

Display device having low voltage differential signal lines overlapping drive circuits

A display device includes a plurality of pixels and drive circuits which drive the plurality of pixels, wherein each drive circuit includes a first input/output terminal, a second input/output terminal, a scanning-direction changeover terminal, and a position designation terminal. In response to a voltage applied to the position designation terminal and a scanning-direction control signal applied to the scanning-direction changeover terminal, the scanning direction is switchable between the first scanning direction which acquires a start pulse from the first input/output terminal and outputs the start pulse from the second input/output terminal and the second scanning direction which acquires the start pulse from the second input/output terminal and outputs the start pulse from the first input/output terminal.

Display device

A liquid crystal display device having a liquid crystal display element having a plurality of pixels. The video signal line driver circuit includes a plurality of amplifiers each of which has a pair of a first input terminal and a second input terminal, and a plurality of pairs of an inverting input terminal and a noninverting input terminal. Each of the plurality of amplifiers has a switching circuit which switches between a first state and a second state, based on a switching control signal supplied with a switching repetition period equal to double a display line repetition period.

A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has: an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to ground; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a dc voltage.

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Mobara, Japan

Yukihide Ode