Shinko Electric Industries Co., Ltd.

Yukiharu Takeuchi

Michio Horiuchi

Hidenori Takayanagi

Toshio Gomyo

Tomoharu Fujii

Yoichi Harayama

Takaharu Yamano

Mohan Kirloskar

Narue Kobayashi

Mitsutoshi Higashi

Kei Murayama

Masahiro Sunohara

Hideaki Sakaguchi

Chiaki Takubo

Shigetsugu Muramatsu

Tadashi Arai

Eiji Yoda

Hiroki Toyazaki

A semiconductor device includes a wiring substrate, a lower magnetic shield member, a semiconductor chip, and an upper magnetic shield member. The lower magnetic shield member is provided on the wiring substrate. The semiconductor chip is provided on the lower magnetic shield member. The semiconductor chip includes a magnetic memory element. The upper magnetic shield member is provided on the semiconductor chip. The semiconductor chip is disposed between the upper magnetic shield member and the lower magnetic shield member. The lower magnetic shield member and the upper magnetic shield member include a soft magnetic resin. The lower magnetic shield member and the upper magnetic shield member are in direct contact with each other.

Semiconductor device having multiple magnetic shield members

A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film.

Lead frame which includes terminal portion having through groove covered by lid portion, semiconductor package, and manufacturing method of the same

A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

Semiconductor device

There is provided a semiconductor device which includes a primary semiconductor chip, a secondary semiconductor chipstacked on the primary semiconductor chip, primary external connecting terminalswhich are electrically connected with the primary semiconductor chipvia wires, secondary external connecting terminalswhich are electrically connected with the secondary semiconductor chipvia wiresand primary and secondary low-elasticity resinswhich seal the primary and secondary semiconductor chipsin such a manner as to cover them.

Semiconductor device, electronic apparatus and semiconductor device fabricating method

A method of manufacturing an electronic parts packaging structure including the steps of preparing a plurality of sheet-like units each of which is constructed by a first insulating layer, a wiring formed on one surface of the first insulating layer, electronic parts connected to the wiring, a second insulating layer formed on an one surface side of the first insulating layer to cover the electronic parts, and a connecting portion for connecting electrically the wiring, and stacking mutually the units to arrange directions of unit adjacent in a thickness direction alternately oppositely, and bonding the units such that electronic parts of respective units are electrically connected mutually via connecting portions.

Method of manufacturing an electronic parts packaging structure

An electronic apparatus includes a multilayer wiring structure having insulating layers and wiring layers which are stacked and having a surface on which an electronic component is mounted, a dipole antenna formed on a surfaceA of the multilayer wiring structure, a radiating plate disposed on the surface together with the dipole antenna, and a radiating path formed in the multilayer wiring structure and serving to transfer a heat generated in the electronic component to the radiating plate.

Electronic apparatus and method of manufacturing the same, and wiring substrate and method of manufacturing the same

In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.

Electronic parts packaging structure

In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Semiconductor device and method of manufacturing the same

In a semiconductor device, via holes are formed around a chip buried in a package, and conductor layers are respectively formed to be connected to one end and another end of the conductor filled in the individual via hole. Portions (pad portions) of the conductor layers which correspond to the conductors are exposed from protective films, or external connection terminals are bonded to the pad portions. The chip is mounted with flip-chip technology so that at least some of electrode terminals thereof are electrically connected to the conductor layers.

A substrate and mask aligning apparatus includes a controlling portionfor calculating moving data that are applied to eliminate a difference between a present superposed state of the through holesof the mask, which comes into contact with the substratethat is loaded on the stage, on the padsof the substrateand a scheduled superposed state on the basis of image data from the shooting sectionand then executing repeatedly an operation to move the stageon the basis of the calculated moving data of the stage.

Substrate and mask aligning apparatus

Package structure having semiconductor device embedded within wiring board

In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Wiring board mounting a capacitor

A lead frame for semiconductor device comprising inner leads, outer leads, and dam bars, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of a semiconductor chip to be mounted on the lead frame, and the inner lead having a first end and a second end, the first ends of the respective inner leads being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads being arranged into arrays at opposed sides of the lead frame, to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged to have lengths between the first and the second ends which are substantially equivalent to each other. A semiconductor device using the lead frame is also disclosed.

Growing community of inventors

Nagano, Japan

Yukiharu Takeuchi