Mitsubishi Electric Corporation

Yuki Yanagihara

Koji Tsutsumi

Mitsuhiro Shimozawa

A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At &#x394;&#x3a3; modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

PLL circuit

A lock detector () detects an unlocked state from an output of a phase frequency comparator (). A counter () counts a reference signal, in a case where an unlocked state is detected by the lock detector (). A parameter controlling circuit () acquires the count value of the counter (), and controls switching on and off of a switch () for a D/A converter () that generates a signal to be added to an output of a loop filter (), and the output voltage of the D/A converter () so that the count value of the counter () falls within a set value.

A first frequency accumulator () operates using an output signal of a variable frequency divider () as a clock. A second frequency accumulator () operates using a reference signal from a reference signal source () as a clock. A comparison operating circuit () compares the output values of the first frequency accumulator () and the second frequency accumulator (), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter () outputs a signal to be added to an output of a loop filter () depending on the parameter output from the comparison operating circuit ().

A setting data output circuit () is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit () which are included in a plurality of dual modulus frequency dividers (-and-) in a first frequency divider group (). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

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Tokyo, Japan

Yuki Yanagihara