Sony Corporation

Sony Semiconductor Solutions Corporation

Yuki Yagishita

Yasunori Tsukuda

Masahiro Segami

To reduce a circuit scale in a successive approximation register analog to digital converter (SARADC) provided with a circuit that cancels a ripple. A digital-to-analog converter generates at least one of a pair of analog signals according to a predetermined control signal. A comparator compares the pair of analog signals and outputs a comparison result. A logic circuit generates a control signal on the basis of the comparison result. A plurality of switches opens and closes a path between one of a source and a drain of each of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes and an output terminal of the comparator on the basis of the control signal. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected in common to each of the gates of the plurality of positive-side transistors. A negative-side capacitor has one end connected to a node of a negative-side reference voltage lower than the positive-side reference voltage, and has the other end connected in common to the gates of each of the plurality of negative-side transistors.

Analog-to-digital converter and electronic apparatus

To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

Comparator and analog to digital converter

A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result. A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.

Comparator and analog-to-digital converter

A detectable range is increased in a radar apparatus that measures a distance from a round-trip time of a sound wave. A transmitting unit transmits a plurality of sound waves including different frequency components in order. A receiving unit receives reflected waves obtained as the plurality of sound waves is reflected. An analyzing unit analyzes a frequency component of each of the reflected waves and identifies, for each reflected wave, the sound wave corresponding to the reflected wave among the plurality of sound waves on the basis of the analysis result. A ranging unit acquires a distance corresponding to a period of time from a transmission time of the sound wave corresponding to the reflected wave to a reception time of the reflected wave.

Radar apparatus, radar system, and radar apparatus control method

To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.

Analog-to-digital converter, electronic device, and method of controlling analog-to-digital converter

An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

Voltage conversion circuit and electronic device

The present technology relates to a semiconductor device that includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block. Further, the power source monitoring circuit is provided with a transistor on a path of a steady-state current, and the steady-state current is inhibited from flowing in accordance with the standby control signal.

Power source monitoring circuit, power on reset circuit, and semiconductor device

A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time.

Voltage conversion circuit and electronic circuit

A phase-locked loop circuit includes: a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison; an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to the error signal; a frequency dividing section configured to generate the comparison clock signal by frequency-dividing the internal clock signal by a predetermined frequency dividing ratio; an oscillator control section configured to generate an oscillation control signal for controlling frequency of the internal clock signal output from the oscillating section on a basis of the error signal; and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of the frequency dividing section on a basis of the error signal.

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Kanagawa, Japan

Yuki Yagishita