The Furukawa Electric Co., Ltd.

Yuki Niiyama

Takehiko Nomura

Seikoh Yoshida

Hiroshi Kambayashi

Yoshihiro Sato

Sadahiro Kato

Masayuki Iwami

Masatoshi Ikeda, Legal Representative

Shinya Ootomo

Hitoshi Sasaki

Nariaki Ikeda

Tatsuyuki Shinagawa

Jiang Li

Shusuke Kaya

Tat-Sing Paul Chow

A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.

Field effect transistor having semiconductor operating layer formed with an inclined side wall

A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A carrier density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode.

Field effect transistor and method of manufacturing the same

Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrodeis provided on the bottom surface or the top surface of the field effect transistor. When the body electrodeis provided on the bottom surface, a p-type GaN layeris provided on a p-type Si substratevia a buffer layercomprising a plurality of AlN layersand GaN layers, with the top layer of that buffer layerbeing a thin AlN layer, and the body electrodebeing formed on the bottom surface of the p-type Si substrate. When the body electrodeis provided on the top surface, a p-type GaN layeris provided on a sapphire substrateand an AlGaN layeris provided on the area under the source electrodeand drain electrode, with the body electrodebeing provided on top of the AlGaN layer. Holesthat are generated by an avalanche phenomenon run through the body electrode

Field effect transistor

Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.

Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor

The laser beam with a wavelength having a higher energy than the band gap energy of the material forming the carrier moving layer is irradiated to activate the impurities contained in the constituent layer of the field effect transistor in the method of producing the field effect transistor. The method of the invention does not apply the heating of the substrate or the sample stage to raise the temperature of the semiconductor layer using the thermal conductivity so as to activate the impurities. Thus, the implanted impurities can be activated without deteriorating the performance of the device and reliability.

Method of producing field effect transistor

An optical absorption layer comprised of a substance having a band gap energy smaller than that of GaN is formed on an implanted region formed in a pGaN layer as a ground layer. There is performed an annealing step from an upper surface of a substrate with predetermined light such as infrared light, a red light, or the like, which has energy smaller than the band gap energy of the pGaN layer. The optical absorption layer has an absorption coefficient of the light in the annealing step larger than that of the pGaN layer. Accordingly, it is possible to selectively perform a heat treatment on a region directly under the optical absorption layer or a region in a vicinity thereof (the implanted region).

Process for producing semiconductor device using optical absorption layer

A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer.

ED inverter circuit and integrate circuit element including the same

The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.

GaN based semiconductor element

A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.

Growing community of inventors

Tokyo, Japan

Yuki Niiyama