Hitachi, Ltd.

Yuki Kuroda

Makoto Saen

Kiyoto Ito

Yasuyuki Kudo

Takeshi Kato

Tatsuya Saito

Masashi Takada

Keisuke Matsumoto

Jun Okitsu

Eiichi Suzuki

Tohru Nojiri

Kozue Fujii

Hirokazu Ogasawara

Keita Sugihara

Yoshio Sonokawa

A cluster system has nodes connected by a first network, including a master node, a first node performing an IO request with respect to a first volume of a storage device capable of including a plurality of volumes through a second network, and a second node taking over processing of the first node at the time of a failure of the first node. When a failure of the first network occurs in the first node, the master node transmits a connection release instruction through the second network. When the connection release instruction is received, the storage device releases the connection between the first node and the first volume, and updates connection state management information for managing such a connection state. The first node acquires the connection state to be managed through the second network, and executes post-processing relevant to the first volume that is associated with the connection release instruction.

Cluster system and fail-over control method of cluster system

Provided is a storage system and a data management method of a storage system enabling system-wide data deduplication. The storage system has a plurality of storage apparatuses in which one or a plurality of logical volumes are provided. Based on data information of data obtained through the generation of a request to write to a logical volume in the storage system, one storage apparatus among the plurality of storage apparatuses calculates, for a plurality of combinations of storage apparatus and logical volume in the storage system, a data capacity when duplicate data is removed for each of the storage apparatuses, calculates the total of the calculated data capacities as the total capacity of the whole storage system, and performs optimal arrangement arithmetic processing to output information indicating a combination with the smallest total capacity among the plurality of combinations.

Storage system and data management method of storage system

Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched. Based on the searched allocation, the workloads are allocated to the information processing devices.

Information processing system, and its power-saving control method and device

It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

Computer and data saving method

In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSIand a memory LSIare stacked and the processor LSIand the memory LSIin the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSIand the memory LSIin the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIsand communication from the processor LSIto the outside are performed by a through silicon via for signalwhich passes through all the LSIs.

Semiconductor device

Semiconductor device with stacked memory and processor LSIs

Growing community of inventors

Musashino, Japan

Yuki Kuroda