Renesas Electronics Corporation

Hitachi, Ltd.

Renesas Technology Corp.

Yuki Kondoh

Isao Ohara

Tohru Nojiri

Makoto Ishikawa

Takashi Matsumoto

Osamu Nishii

Tatsuya Kamei

Hiroaki Nakaya

Toru Nojiri

Katsuto Sato

Keisuke Toyama

An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.

Information processing device and processor

A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.

Computer and computer system for collision determination of a command identifier

A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Computer system, server module, and storage module

The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Semiconductor device with instruction code and prefix code predecoders

This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.

Data processor with interfaces for peripheral devices

A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (), each running an application program under controls of different operating systems, and a virtual machine manager () for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (); and a resource access management module () for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.

Data processor with virtual machine management

The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.

Data processor

A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.

Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements

A device with a small number of circuits is provided for blocking illegal address access from a bus master device connected to the processor system bus. An illegal address blocking circuit is inserted into the address line and control lines between the bus master device and the bus or the bus control circuit, according to the system bus configuration. A register is installed within the illegal address access blocking device to set an address range where access is allowed. The address output from the address line is then checked by a comparator to find if it is within the allowable range or not, and if it is outside the allowable range, then that illegal access is prevented by blocking the output on the control line.

A semiconductor data processor has a first memory() constituting a cache memory, a second memory() capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer() capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

Semiconductor data processor

The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

Growing community of inventors

Hino, Japan

Yuki Kondoh