Tokyo Electron Limited

Tokyo Electron Limi Ted

Yuki Kikuchi

Kaoru Maekawa

Akiteru Ko

Toshiharu Wada

Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

Methods to reduce gouging for core removal processes using thermal decomposition materials

Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

Methods to reshape spacers for multi-patterning processes using thermal decomposition materials

A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

Method to transfer patterns to a layer

Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.

Self-aligned interconnect patterning for back-end-of-line (BEOL) structures including self-aligned via through the underlying interlevel metal layer

A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

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Albany, NY, United States of America

Yuki Kikuchi