Kioxia Corporation

Toshiba Memory Corporation

Toshiba Memory Corportion

Yuki Inuzuka

Takayuki Miyazaki

Takeshi Sugimoto

Tsuneo Inaba

Katsuaki Isobe

Takaaki Nakazato

Shingo Nakazawa

Yoshinori Suzuki

A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.

Semiconductor storage device

A memory includes first and second wires. First and second transistors are connected to the first wires and transfer a first and second voltage. Third and fourth transistors are connected to the second wires and transfer the first and second voltages to the second wires. A first memory cell includes a first diode and a first memory element connected in series. The first diode is connected so that a forward bias direction thereof is from the one first wire to the first signal line. A second memory cell includes a second diode and a second memory element connected in series. The second diode is connected so that a forward bias direction thereof is from the second signal line to the one first wire.

A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.

Semiconductor storage device and program operation method for a select gate line of the semiconductor storage device

A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.

Semiconductor device

The semiconductor memory device of the embodiment includes: a substrate; a first memory pillar extending in a first direction from the substrate, the first memory pillar including first memory cell transistors, a first selection transistor, a second selection transistor, second memory cell transistors, a third selection transistor, a fourth selection transistor, third memory cell transistors, a fifth selection transistor, a sixth selection transistor, fourth memory cell transistors, a seventh selection transistor, and an eighth selection transistor; a first select gate line; first word lines; a second select gate line; a third select gate line; second word lines; a fourth select gate line; a fifth select gate line; third word lines; a sixth select gate line; a seventh select gate line; fourth word lines; and an eighth select gate line.

Semiconductor memory device

A semiconductor memory device includes a first semiconductor pillar having i first memory cells on a first side and i second memory cells on a second side, a second semiconductor pillar having i third memory cells on a third side and i fourth memory cells on a fourth side, i first word lines (i is an integer of 4 or more) connected to the i first memory cells and the i third memory cells, i second word lines connected to the i second memory cells and the i fourth memory, and a driver. In writing data to the k-th (k is smaller than i and greater than 1) first memory cell, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage.

Semiconductor memory device in which data writing to cells is controlled using program pulses

A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.

A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.

Semiconductor storage device and method of reading data therefrom

According to one embodiment, a semiconductor memory device, includes a resistance change type memory cell; a first charge section into which a charge based on a current flowing in the memory cell is charged; a second charge section coupled to the first charge section via a switch element; a sense amplifier configured to determine data stored in the memory cell based on the charge charged into the second charge section; and a control circuit configured to control the first charge section, the second charge section, and the sense amplifier.

A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

Resistance change type memory

A semiconductor memory device includes a memory cell array with bit lines and word lines connected thereto. A first power supply circuit generates a selected bit line voltage. A second power supply circuit generates a non-selected bit line voltage. A third power supply circuit generates a selected word line voltage. A fourth power supply circuit generates a non-selected word line voltage. A first decoder connects the selected bit line to the first power supply circuit and connects the non-selected bit line to the second power supply circuit. A second decoder connects the selected word line to the third power supply circuit and connects the non-selected word line to the fourth power supply circuit. A capacitive element is between a first node that is between the second power supply circuit and the first decoder and a second node that is between the third power supply circuit and the second decoder.

Growing community of inventors

Yokohama Kanagawa, Japan

Yuki Inuzuka