Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Yuki Fujimura

Ichiro Seto

Shigehito Saigusa

Yousuke Hagiwara

Mitsuyuki Ashida

Hiroyuki Kobayashi

Jun Deguchi

Osamu Hirabayashi

Masahiro Sekiya

Koji Horisaki

Takahiko Sasaki

Hideaki Majima

Toshiyuki Yamagishi

Yasuhisa Takeyama

Nau Ozaki

Hideki Yamada

A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fto a transmitter and up-converting the test signal with a frequency fand down-converting with the frequency f. A frequency 2fcomponent is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fcomponent in the test signal.

Carrier leakage correction method for quadrature modulator

According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.

Communication device and orthogonal error measurement method for communication device

According to one embodiment, a transmission system includes a transmitter and a receiver. The transmitter includes a modulator configured to modulate transmission data at a chip rate to generate a modulation signal, and one or a plurality of light sources configured to emit visible light according to the modulation signal. The receiver includes a light receiver having one or more lines of light receiving elements to receive light in a first range including the visible light; and a demodulator configured to demodulate image data generated according to the light received by the light receiver to generate reception data corresponding to the transmission data. A following equation is satisfied ff&#x3c;fm where fm is the chip rate, and ff is a frame rate of the light receiver.

Transmission system, transmitter and receiver

According to one embodiment, a bit line negative potential circuit includes a bit line capacitance compensation capacitor which compensates the capacitance of a bit line and a peripheral capacitance compensation capacitor which compensates the peripheral capacitance of the bit line. After the bit line is switched to a low potential, the bit line is driven based on a charging voltage of the bit line capacitance compensation capacitor and the peripheral capacitance compensation capacitor.

Bit line negative potential circuit and semiconductor storage device

A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.

Semiconductor storage device

Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connected to the power supply node. The variable capacitance circuit includes: second and third metal interconnections electrically connected to a connection node; and a controller capable of controlling electrical connection between the third metal interconnection and the connection node. The connection switch is connected between the first metal interconnection and the connection node of the variable capacitance circuit. The connection switch is configured to electrically connect the first metal interconnection and the connection node in a write operation of the memory cell.

Static random access memory

Growing community of inventors

Ota Tokyo, Japan

Yuki Fujimura