Mitsubishi Denki Kabushiki Kaisha

Yukari Watanabe

Yuichi Saito

Toyohiko Yoshida

Masahito Matsuo

Toru Shimizu

This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Multiple sequentially transferrable stackpointers in a data processor in

A high-speed encoding apparatus retrieves the bit position of either one of the lowest order bit or the highest order bit having a first logical value. Such retrieving starts from a selected bit-position. The selected bit-position is defined by an input offset value Iofs4:Iofs0. The retrieved bit-position is the output of the encoder Oofs4:Oofs0. A zero detection circuit receives an n-bit data word, segments the n-bits into groups of predetermined length and for each group generates a zero detection when all bits in the group are zero. The zero detection circuit also masks the zero detections according to the high order bit states of the input offset value. A first encoder then generates the high order bits of the apparatus output offset in response to the masked and unmasked zero detections. A second encoder masks one or more of the groups according to the bit states of the input offset value, then generates encoded bit sets for each group. The high order bits of the output offset previously generated then are used to select which of the bit sets are used as the low order bits of the output offset.

Encoder apparatus

This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

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Itami, Japan

Yukari Watanabe