Kabushiki Kaisha Toshiba

Yukari Unno

Fumitomo Matsuoka

Hiroshi Momose

Masataka Matsui

Takeo Maeda

A polycrystalline silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the polycrystalline silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polycide gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten silicide layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten silicide layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten silicide layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer. In the manufacturing method as described above, an ohmic contact can be realized between the polycide gate electrode and the diffusion layer via the tungsten silicide layer, irrespective of the conductivity types of the gate electrode and the diffusion layer, without use of any additional metallic layer other than the polycide.

Semiconductor device having gate electrode and impurity diffusion layer

A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer. In the manufacturing method as described above, an ohmic contact can be realized between the polyside gate electrode and the diffusion layer via the tungsten siliside layer, irrespective of the conductivity types of the gate electrode and the diffusion layer, without use of any additional metallic layer other than the polyside.

Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line drive circuits located near the memory cell array. Each of the word-line drive circuits is a Bi-NMOS circuit which comprises a bipolar transistor for pulling up the potential of the word line and an N-channel MOS transistor for pulling down the potential of the word line. The collector layers of the bipolar transistors are formed of one and the same layer.

Bi-CMOS semiconductor integrated circuit

At least part of a low impurity concentration collector region which lies between the emitter and collector regions of a bipolar transistor in a Bi-CMOS device is formed to have a low impurity concentration. Therefore, a high emitter-collector withstanding voltage can be obtained. Further, at least part of the low impurity concentration collector region which lies between the base region and an opposite conductivity type region is formed to have a high impurity concentration. Therefore, the punch-through withstanding voltage of a parasitic transistor formed of the base, collector and, opposite conductivity type region can be enhanced, and, at the same time, the collector resistance can be reduced.

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Yokohama, Japan

Yukari Unno