Mitsubishi Denki Kabushiki Kaisha

Yukari Hiratsuka

Kazuhiro Sugiyama

Noboru Yashima

Naoki Kizu

For recording data on and reproducing data from an optical disk of a single spiral land/groove configuration, a header detector detects header regions on the optical disk, a PID error detector judges whether the address information read from the header regions is erroneous, using error detection codes, and detects the number of errors per sector. An error count comparator compares the number of errors per sector with a predetermined value, and a state judging circuit identifies the state of the optical disk device by causing transition to a higher or lower state according to the output of the error count comparator. The recording and reproduction are controlled according to the state thus identified.

State detecting device and optical disk device

In a device for controlling rotation of a disk, if a determination is made that a signal is not normally detected by a pre-pit-region detection circuit, an error signal is obtained from a pulse generator to control the rotation of the disk. If a determination is made that a signal is normally detected by the pre-pit-region detection circuit and if the synchronizing signals are not normally detected at predetermined intervals, an error signal is obtained from the wobble signal so that the rotations of the disk are controlled. If a determination is made that synchronizing signals are detected by the pre-pit-region detection circuit at predetermined intervals, an error signal is obtained from clocks synchronized with the reproduced signal generated by the PLL circuit so that rotations of the disk are controlled.

Disk-rotation control apparatus

A data recorder for recording data onto a record medium on which a sync signal is inserted at a given interval, has a sequence controller, wherein, after receiving the command from the system controller which triggers an initiation of a recording operation, the sequence controller activates the first encoder in response to a leading end signal of the encoded block from the sync signal set-up section, activates the first encoder and the second encoder in response to a leading end signal of the next encoded block, and activates the first encoder, the second encoder and the data reader in response to a leading end signal of the next following encoded block, and wherein, during the absence of the command from the system controller which triggers an initiation of a recording operation, the sequence controller deactivates the first encoder in response to a leading end signal of an encoded block from the sync signal set-up section, deactivates the first encoder and the second encoder in response to a leading end signal of the next encoded block, and deactivates the first encoder, the second encoder and the data reader in response to a leading end signal of the next following encoded block.

Data recorder and data producing circuit

When a detected value of the signal processing speed from a frequency comparator is larger than a prescribed value input from an input terminal, the rotation control of a disk is switched from constant linear velocity control to constant angular velocity control using an error signal from an arithmetic unit. Alternatively, when a detected value of the rotational velocity from a frequency comparator is larger than a prescribed value input form an input terminal, the rotation control of the disk is switched from the constant angular velocity control into the constant linear velocity control.

Disk rotation control device

If a determination is made that a signal is not normally detected by the pre-pit-region detection circuit 53, an error signal is obtained from a pulse generator 58 to control the rotations of the disk 50. If a determination is made that a signal is normally detected by the pre-pit-region detection circuit 53 and if the synchronizing signals are not normally detected at predetermined intervals, an error signal is obtained from the wobble signal so that the rotations of the disk 50 are controlled. If a determination is made that synchronizing signals are detected by the pre-pit-region detection circuit 53 at predetermined intervals, an error signal is obtained from clocks synchronized with the reproduced signal generated by the PLL circuit 54 so that rotations of the disk 50 are controlled.

An MPEG audio decoder has an irregular-pattern processing circuit for detecting irregular patterns in the bit stream input to the decoder, and altering these irregular patterns, or altering data or signals derived from these irregular patterns, so that the irregular patterns do not cause annoying defects in the audio signal output from the decoder. The alteration may take the form of replacement by a minimum value, or interpolation of a preceding value.

MPEG audio decoder for detecting and correcting irregular patterns

A sub-band audio signal synthesizer produces a digital audio signal from a sub-band coded audio signal having a predetermined number of sub-bands. A memory stores predetermined samples. A memory controller controls read and write operations of the memory. An adder adds the signal read out of the memory to a new window signal produced on the sub-band coded audio signal to synthesize a digital audio signal. A buffer memory stores and outputs the synthesized digital audio signal and an interpolation signal of the digital audio signal. During normal synthesis, the memory-controller cyclically reads the samples stored in the memory beginning from an address shifted by a predetermined number of samples every time a new cycle of reading is started. The memory-controller writes a result of the addition by the adder back into the memory, thereby producing cumulatively added samples of the window signals. The output circuit outputs, from among the cumulatively added samples, a predetermined number of samples which have been subjected to a predetermined number of cumulative additions, the sample being outputted every time the addition is performed. During interpolation, the memory-controller prevents the result of the addition from being written into the memory, and repeatedly reads the cumulatively added samples from the memory. The output circuit outputs the cumulatively added samples read from the memory as the interpolation signal of the digital audio signal.

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Tokyo, Japan

Yukari Hiratsuka