Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Amazon Technologies, Inc.

Dongwoo Fine-chem Co., Ltd.

Techcross Co. Ltd.

Yujin Kim

Bio Kim

Junggeun Jee

Byungseok Choi

Kyong-Won An

Myung-Eun Kim

Jaehyun Yang

Sookyeom Yong

Youngjun Cheon

Hyung Joon Kim

Sangil Kim

Woojin Jang

Jeehoon Kim

Shinhyuk Yang

Shin Tack Kang

Kunhee Jo

Jeongbong Lee

Jumi Yun

Donghan Kang

Shintack Kang

Yeuntae Kim

Eunyeoung Choi

Youngseon Son

Kyongwon An

Hyunseok Kim

Philouk Nam

Youngmin Kim

Sang-Il Kim

Haeil Park

Seok-Joon Hong

Soyeon Park

Joo-Han Bae

Hyung-Il Jeon

Kap Soo Yoon

Hajin Song

Gwangsoo Ahn

Taehyeong An

Jimyoung Seo

Gilhwan Yeo

Yousik Shin

Beomsoo Kim

Youngjin Yoon

Seongtae Kim

Gyuhun Han

Kyuwon Park

Haidon Lee

Dasom Kang

Hyeonsu Cho

Eunwon Lee

Hongkyu Kim

Poyun Park

Yongseok Park

Daewon Kim

Kisung Lee

Jahun Ku

Soonwook Hong

Hanhee Yoon

Hyeyoung Ryu

A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

Three-dimensional semiconductor memory devices

An etchant including: persulfate; a fluorine-containing compound; a chlorine-containing compound; a cyclic amine compound; an inorganic acid; sulfate; and water, wherein a tip control index (Y) of the etchant is a value of at least about 45.0 and not more than about 70.0, the tip control index (Y) being a value calculated by Equation 1:=1.0×10(1)+1.0×10(2)+5.0×10(3)+1.5×(1)×(2)+2.0×10(1)×(3)+2.0×10(2)×(3)  Equation 1The description of Equation 1 is as in the specification.

Etchant

A display panel includes: a window including a display area, and a non-display area adjacent to the display area; a color filter layer on the window; a circuit element layer including: a low refractive index layer covering the color filter layer; and a transistor on the low refractive index layer; a light control layer including: division partition walls on the circuit element layer; and a light control pattern between the division partition walls, and including quantum dots; and a display element layer on the light control layer, and including: a first electrode; a second electrode on the first electrode; and an emission layer between the first electrode and the second electrode and to generate light. The light passes through the light control layer, the circuit element layer, and the color filter layer to be transmitted to the window.

Display panel and method for fabricating the same

A display panel including: a display region including pixels and a non-display region, each pixel including an emission element including a first electrode, an emission layer, and a second electrode; a pixel definition layer including a first opening; a first encapsulation layer on the pixel definition layer and overlapping the emission element; a partition wall on the first encapsulation layer and including a second opening and a dummy opening; a light control pattern in the second opening; a second encapsulation layer on the partition wall and overlapping the light control pattern; and a color filter on the second encapsulation layer and overlapping the light control pattern, the second encapsulation layer includes: a first encapsulation inorganic layer on the partition wall; an encapsulation organic layer on the first encapsulation inorganic layer and including an edge overlapping the dummy opening; and a second encapsulation inorganic layer on the encapsulation organic layer.

Display panel

A display apparatus includes: a substrate including a display area, and a peripheral area; and a pad unit at the peripheral area, the pad unit including: a first conductive layer; a second conductive layer on the first conductive layer, and having a first opening; a third conductive layer on the second conductive layer, and having a second opening overlapping with the first opening, the second opening having an area less than an area of the first opening at a top surface of the second conductive layer; an organic protective layer filling the first opening, and having a third opening overlapping with the second opening; and an additional metal layer covering a top surface of the first conductive layer exposed through the first opening, an inner surface of the second opening, an inner surface of the third opening, and a portion of a top surface of the third conductive layer.

Display apparatus including pad unit having plurality of conductive layers with multiple openings

A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

Vertical memory devices and methods of manufacturing the same

A method of manufacturing a display apparatus includes: forming a display element layer above a lower substrate, where the display element layer includes first to third display elements; forming an encapsulation layer on the display element layer; forming first partition walls on the encapsulation layer to define first to third color regions, where the first to third color regions overlap the first to third display elements, respectively, in a view in a direction perpendicular to the lower substrate; forming second partition walls on the first partition walls; forming a quantum dot layer, which includes forming a second color quantum dot layer in the second color region and forming a third color quantum dot layer in the third color region; and removing the second partition walls.

Display apparatus comprising partition wall and quantum dot layer

Method of manufacturing display apparatus

A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

Semiconductor device including partially enlarged channel hole

A display device includes: a substrate; a touch electrode disposed on the substrate; a routing wiring disposed on the touch electrode; a light blocking layer disposed on the touch electrode; a semiconductor layer disposed on the light blocking layer; a source electrode and a drain electrode spaced apart from each other and disposed on the semiconductor layer; and a gate electrode disposed on the source electrode and the drain electrode.

Display device and manufacturing method of the same

A method of driving a display device includes receiving a reference clock signal and frequency determination data to determine a pixel driving clock frequency and generate a pixel driving clock signal, generating and outputting a gate driving clock signal according to the pixel driving clock frequency, and outputting a driving voltage according to the pixel driving clock frequency. The driving voltage increases as the pixel driving clock frequency increases.

Display device and a method for driving the same

Growing community of inventors

Suwon-si, South Korea

Yujin Kim