Arizona State University

Yuji Zhao

Houqiang Fu

Kai Fu

Xuanqi Huang

Chen Yang

Hugh Barnaby

Runchen Fang

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiOhard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiOhard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

GaN vertical-channel junction field-effect transistors with regrown p-GaN by metal organic chemical vapor deposition (MOCVD)

Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

Low-leakage regrown GaN p-n junctions for GaN power devices

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

GaN-based threshold switching device and memory diode

A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.

Plasma-based edge terminations for gallium nitride power devices

A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.

Steep slope transistors with threshold switching devices

An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of &#x2dc;10, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.

Growing community of inventors

Chandler, AZ, United States of America

Yuji Zhao