Shinko Electric Industries Co., Ltd.

Yuji Yukiiri

Izumi Tanaka

Natsuko Kitajo

Yoji Asahi

Natsuko Ueda

An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.

Interconnect substrate and method of making the same

A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.

Wiring substrate

A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.

Wiring substrate and semiconductor device

There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.

Method for manufacturing wiring board

A multilayer wiring substrate having no core substrate is provided. The multilayer wiring substrate includes: a laminated body includes: a plurality of insulating layers; and a plurality of wiring layers. The laminated body has: a mounting surface on which a semiconductor element is mounted; and a bonding surface to which external connection terminals are bonded. At least one of the insulating layers contains a glass cloth.

Multilayer wiring substrate with a reinforcing layer for preventing a warp

A method for cleaning a surface of a resin layer capable of sufficiently improving peel strength of a metal film formed by plating on a surface which is roughened by performing a desmear treatment on a resin layer containing a resin added with a large amount of filler is provided.

Growing community of inventors

Nagano, Japan

Yuji Yukiiri