Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Yuji Yokoyama

Yutaka Kobayashi

Masahiro Iwamura

Tatsumi Yamauchi

Takashi Akioka

Atsushi Hiraishi

Akira Ide

Shigeru Takahashi

Shuichi Miyaoka

Hideaki Uchida

Nobuyuki Gotou

Toru Kobayashi

Nozomu Matsuzaki

Michiaki Nakayama

Hiroshi Akasaki

Hideki Sakakibara

Noboru Akiyama

Masatoshi Hasegawa

Kozaburo Kurita

Hideo Sawamoto

Kunihiko Suzuki

Masahiro Yamamura

Tatsuyuki Ohta

Masaji Kume

Hitoshi Miwa

Kazuyuki Miyazawa

Tsugio Takahashi

Mitsugu Kusunoki

Shoji Wada

Yousuke Tanaka

Toshio Shinomiya

Masahiro Katayama

Koichi Motohashi

Akimitsu Mimura

Akio Koyama

Atushi Hiraishi

Masayoshi Nomura

Kazumasa Takashima

Nobutaka Itoh

In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit.

Semiconductor integrated circuit device

In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle

Read buffers (RB -RB ) are capable of holding data read out from a plurality of memory blocks (BNK -BNK ) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means ( ) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface

The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK to MBKn). A plurality of serial data readout from the memory cell array ( ) and parallel/serial converted by a parallel/serial converter circuit ( ) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit ( ) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal

Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting

An oscilator circuit for a integrated circuit memory device to optimize the refresh operating circuit and suppress wasteful power consumption in which the oscillator frequency is set high during high temperatures and the oscillator frequency is set low during low temperatures. A current I,is generated by means of the current source,having characteristics in which it is increased during high temperatures and decreased during low temperatures, and is supplied to the ring oscillator,. A current corresponding to the current I,is supplied to each inverter in the frame oscillator,, and since the oscillator frequency is controlled by means of the current value of the supplied current, the frequency of the clock signal CLK generated increases accompanying a rise in temperature, and since the refresh operation is conducted based on the clock signal CLK, the data holding capabilities can be ensured during high temperatures, wasteful power consumption can be reduced during low temperatures, and optimization of the refresh operating frequency can be realized.

Oscillator circuit for a semiconductor memory having a temperature dependent cycle

A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers

A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.

Semiconductor memory device having a redundancy capability

A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Signal transition detector circuit

An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Semiconductor integrated circuit having logi gates

A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data; a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.

Pipeline-operating type memory system capable of reading data from a

A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Semiconductor device

A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data, a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.

An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Semiconductor integrated circuit having logic gates

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Ome, Japan

Yuji Yokoyama