Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Electronics Engineering Co., Ltd.

Hitachi-High-Technologies Corporation

Yuji Wada

Ryuji Kohno

Yasuhiro Motoyama

Susumu Kasukabe

Terutaka Mori

Masaaki Namba

Naoto Ban

Makoto Kitano

Kunio Matsumoto

Tetsuo Kumazawa

Hidetaka Shigi

Akihiko Ariga

Takayoshi Watanabe

Shuji Shibuya

Akio Hasebe

Akira Seito

Hideo Miura

Yoshishige Endo

Tatsuya Nagata

Masatoshi Kanamaru

Yasunori Narizuka

Hiroya Shimizu

Akira Yabushita

Atsushi Hosogane

Takehiko Hasebe

Toshio Miyatake

Teruo Shoji

Masaaki Mochiduki

Masakazu Sueyoshi

Takeshi Wada

Hideyuki Aoki

Makoto Yanagawa

Keiji Muraju

Yoshio Kamiko

Kaoru Fukuda

Noboru Uchida

Shigeki Katsumi

A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Fabrication method of semiconductor integrated circuit device

A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

Method and apparatus for testing a memory device in quasi-operating conditions

The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step

A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

Packaging device for holding a plurality of semiconductor devices to be inspected

A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

Fabrication method of semiconductor integrated circuit device and its testing apparatus

Method for producing semiconductor device and apparatus usable therein

Contact ring, which is brought into contact with a probe card having tungsten needles, has a multiplicity of POGO pins on its one surface facing the probe card. The contact ring has, on another surface opposite to the one surface, press-fitting sockets electrically connected with the POGO pins. Motherboard has sockets similar in construction to the press-fitting sockets of the contact ring. Coaxial cables each have press-fit terminals that are press-fittable in one of the sockets of the contact ring and in one of the sockets of the motherboard, and thereby these coaxial cables electrically connect the contact ring with the motherboard. Because the contact ring and the motherboard are electrically connected with each other by the press-fit engagement alone, there are encountered no inconveniences due to the conventional soldering-based connection.

Interface unit for a tester and method of connecting a tester with a semiconductor device to be tested

Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

Main tester unit tests an IC device for presence of a defect for each of a plurality of addresses of the IC device under predetermined test conditions and stores test results for the individual addresses into a first memory. Curing analysis processing section cures each of the addresses of the IC device determined as defective, on the basis of the test results for the individual addresses stored in the first memory. To this end, the curing analysis processing section may rearrange an address logic of the IC device to replace a physical space of the defective addresses with an extra or redundant address space and thereby place each of the defective addresses in a usable condition. In parallel with the operations by the curing analysis processing section, a defect analysis section acquires, from the main tester unit, the test results for the individual addresses along with data indicative of the predetermined test conditions for storage into a second memory, and analyzes a specific cause of the defect in the IC device on the basis of the stored data in the second memory. With this arrangement, it is possible to acquire information necessary for analyzing the defect in the IC during a curability determining analysis test on a mass production line and thereby can effectively analyze the specific cause of the detected defect.

IC testing apparatus and method

Growing community of inventors

Tachikawa, Japan

Yuji Wada