Fujitsu Corporation

Yuji Tsuchimoto

Yasurou Matsuzaki

Kouji Ueno

Masaki Takahashi

Yoshiyuki Fujita

Yoshikazu Mutoh

A programmable memory device includes memory cells arranged at cross points of word lines and bit lines, a selecting part for selectively decreasing potentials of the word lines, and a writing part for selectively supplying programming currents to the memory cells via the bit lines. Programming current absorbing transistors have first terminals respectively connected to the word lines, second terminals set at a predetermined potential, and bases, and a common load element connected between a node and a programming voltage line. A plurality of base current supplying circuits, which are respectively coupled to the programming current absorbing transistors and connected in common to the node, turn ON the programming current absorbing transistors related to word lines selected by the selecting part so that base currents pass from the programming voltage line to the bases of the programming current absorbing transistors via the common load element and the base current supplying circuits.

Programmable memory device having programming current absorbing

An address transition detector circuit detects a transition of an address signal. The address transition detector circuit has a first circuit part which includes two field effect transistors which are coupled in series and simultaneously turn ON when an address transition is detected, and a second circuit part which includes a bipolar transistor for discharging so that a transition detection signal changes its level immediately after the address transition is detected in the first circuit part.

Address transition detector circuit

A programmable semiconductor memory circuit comprises a memory cell array, a write circuit which is driven by a first power source voltage only in a write mode for writing data into memory cells of the memory cell array, an address input circuit which is driven by a second power source voltage for supplying an address signal to the memory cell array, and an input level correcting circuit supplied with the first power source voltage only in the write mode for supplying the first power source voltage to the address input circuit. The second power source voltage has a voltage higher in the write mode than in a read mode. The address input circuit has an arrangement such that an input threshold value thereof changes when the second power source voltage changes. The input level correcting circuit supplies the first power source voltage to the address input circuit to pull up a signal level at an input of the address input circuit in the write mode so that a signal having a high logic level at the input of the address input circuit is greater than the input threshold value of the address input circuit.

Programmable semiconductor memory circuit

A read only memory circuit comprises bit lines, word lines and cells connected between the bit lines and word lines. The read only memory circuit also comprises a discharge circuit. The discharge circuit is used for discharging all the bit lines except for one of the bit lines designated in order to read out a datum stored in a cell connected to the designated one bit line.

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Kawasaki, Japan

Yuji Tsuchimoto