Sony Corporation

Sony Semiconductor Solutions Corporation

Yuji Torige

Yasuo Kanda

Koichi Amari

Takayuki Arima

Shunsaku Tokitou

Takafumi Kunihiro

Shunsaku Tokito

Takuya Kurihara

Provided is a technology capable of acquiring a saturation charge amount and improving low-light characteristics while suppressing an enlargement of a device and deterioration in pixel density. A solid-state imaging device according to an embodiment includes: a first substrate () including a plurality of photoelectric converters (PD) arranged in a matrix; a second substrate () that is bonded to a first surface of the first substrate and includes a pixel circuit () that generates a pixel signal based on a charge generated in each of the photoelectric converters; and a third substrate () bonded to a third surface of the second substrate opposite to a second surface to which the first substrate is bonded, the third substrate including a peripheral circuit that executes predetermined processing on the pixel signal generated by the pixel circuit, in which the pixel circuit includes: a charge accumulation unit (FD) that accumulates a charge generated in the photoelectric converter; an amplification transistor (AMP) that generates the pixel signal having a voltage value corresponding to a charge amount regarding the charge accumulated in the charge accumulation unit; and a switching transistor (FDG) that switches capacitance of the charge accumulation unit.

Solid-state imaging device and electronic device

A semiconductor circuit includes first (IV, IV) and second (IV, IV) circuits, first () and second () transistors, a first storage element (), and a driver (). The first (IV, IV) and second (IV, IV) circuits, respectively, apply inverted voltages of voltages at first (N) and second (N) nodes to the second (N) and first (N) nodes. The first transistor () is turned on to couple the first (N) and third nodes. The second transistor () includes a gate coupled to the first node (N), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL). The first storage element () includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element () is able to take a first or second resistance state. The driver () controls operation of the first transistor () and generates the first (SCL) and second (SCTRL) control voltages.

Semiconductor circuit, driving method, and electronic apparatus

A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.

A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Semiconductor circuit, method of driving semiconductor circuit, and electronic apparatus

A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.

Memory element, semiconductor device, and writing method

A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Semiconductor device having an electrical fuse element

An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer.

Electric fuse, semiconductor device, and information writing method of electric fuse

Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell arrayhas a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRBand TRB) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRBand TRB), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit(and a word line drive circuit).

Growing community of inventors

Kanagawa, Japan

Yuji Torige