Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Yuji Takizawa

Haruo Yamashita

Kazuyuki Tajima

Masaaki Kawai

Hidetoshi Naito

Kazuo Yamaguchi

Satomi Ikeda

Hisako Watanabe

Hideo Tatsuno

Masayoshi Sekido

A fault recovery system of a ring network based on a synchronous transport module transmission system, having a fault data writing unit for writing, when an input fault is detected by a node, fault data in a predetermined user byte in an overhead of a frame flowing through both a working line and a protection line running in opposite directions to each other. By detecting the fault data in a supervision node or a node just before the fault position, the supervision node or the node just before the fault position executes a loopback operation.

Fault recovery system of a ring network

A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from the first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit, and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.

Transmission circuit for transmitting fixed-length data

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

Asynchronous signal extracting circuit

A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

System for monitoring ATM cross-connecting apparatus by inside-apparatus

Growing community of inventors

Kawasaki, Japan

Yuji Takizawa