Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporaton

Yuji Takai

Daisuke Murakami

Takahide Baba

Yoshiharu Watanabe

Isao Kawamoto

Seiji Horii

Toshihiro Fukuyama

Michihiro Matsumoto

Tetsuji Kishi

Masanobu Mizuno

Yuki Soga

Kazue Nakatani

Yasuo Nishioka

A memory device () includes a memory device controller (), a delay adjustment storage unit () configured to store timing adjustment data which is read as both values 0 and 1 at a rise and a fall of a strobe signal, a memory cell (), and a selector () configured to switch connection to the delay adjustment storage unit or the memory cell. A memory interface () reads the timing adjustment data of the delay adjustment storage unit () while changing the timing to search for a read timing range, and selects and sets read timing from the timing range.

Memory device, memory system, and access timing adjusting method in memory system

A clock enable (CKE) control circuit () is provided between a memory control circuit () and a SDRAM (). When a system is in, e.g., a sleep state, the CKE control circuit () controls a CKE signal outputted to the SDRAM () such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM (), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM ().

Memory control device

A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.

System and method for bus transmission cancellation

An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Resource management device

A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Resource management device for managing access from bus masters to shared resources

A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.

Simulator of logic circuit and simulation method

By means of tables, characters, and the like displayed on the screen of a CRT monitor, a functional diagram editor element can generate, on the screen of the CRT monitor, a functional diagram for representing the operation of a logic circuit. A functional diagram check element detects the presence or absence of a contradiction in the generated functional diagram. Furthermore, a functional simulation element can perform the functional verification of the functional diagram free from contradiction. A hardware-description-language conversion element can generate a hardware description language from the functional diagram in which the circuit operation has undergone error correction. A logic synthesis element can generate netlist information from said hardware description language.

Growing community of inventors

Osaka, Japan

Yuji Takai