Sony Computer Entertainment Inc.

Sony Corporation

Canon Kabushiki Kaisha

Fuji Photo Film Company, Limited

International Business Machines Corporation

Sony Semiconductor Solutions Corporation

Kabushiki Kaisha Toshiba

Honda Giken Kogyo Kabushiki Kaisha

Toshiba Machine Co., Ltd.

Yuji Suzuki

James Allan Kahle

Charles Ray Johns

Seiji Wada

Koji Kashima

Yoshihiro Wakita

Scott Douglas Clark

Tomochika Murakami

Natsuki Kimura

Syunji Kumamoto

Harm Peter Hofstee

Junichi Hayashi

Yusuke Otake

Hideharu Nakajima

Yuji Kawamura

Hideki Arai

Takuro Murase

Fumio Yuito

Makoto Sato

Hiroshi Hayashi

Michael Norman Day

Mitsuhiro Nakamura

Atsushi Kunimatsu

Peichun Peter Liu

Nobuo Sasaki

Hiroshi Kajiwara

Tatsumi Sakaguchi

Jeffrey Douglas Brown

Tsutomu Imoto

Hidefumi Osawa

Hiroki Kishi

Tomiji Tanaka

Takuya Maruyama

Tetsuomi Tanaka

Ryota Watanabe

Tsutomu Horikawa

Takuro Yamamoto

Yasuhiro Iizuka

Haruhiko Soma

Yuji Isogai

Fumio Noji

Tai Nakashima

Yoshiaki Kashio

Sangman Han

Katsushi Ohtsuka

Taisuke Suwa

Sanshiro Fukuhara

Motofumi Kashiwaya

Hideki Yasukawa

Giichiro Akimori

Shigehisa Morinaka

Kazuo Morishima

Hiromu Saijo

Nobuyuki Hayabusa

Koichi Kanazawa

Nobuyuki Yoshida

The present technique relates to an imaging element and a distance measurement module capable of reducing parasitic capacity. A distance measurement module includes: a first wiring that connects predetermined transistors in first adjacent pixels to a via formed in one of first adjacent pixels and connected to a wiring formed in another layer; and a second wiring that connects predetermined transistors in second adjacent pixels to a via formed in a pixel that is adjacent to one of second adjacent pixels and connected to a wiring formed in another layer, in which the first wiring is connected to a redundant wiring. The present technique can be applied to a distance measurement sensor that performs distance measurement, for example.

Imaging element and distance measurement module

There is provided a light-receiving element that includes a semiconductor substrate, a light-shielding film provided on a first surface of the semiconductor substrate and having a lattice form in which openings are arrayed in a matrix form, a plurality of first semiconductor regions arrayed in a matrix form on a second surface opposite to the first surface of the semiconductor substrate, a plurality of second semiconductor regions provided in an adjacent region which is the second surface of the semiconductor substrate and interposes each of the first semiconductor regions in a column direction, and a wiring layer provided on the second surface of the semiconductor substrate and electrically connected to the first semiconductor regions. The first semiconductor region is located in a corresponding region with the light-shielding film and the first surface of the semiconductor substrate interposed therebetween.

Light-receiving element, solid-state imaging device, and ranging device

The present technology relates to an image sensor, an imaging device, and a ranging device capable of performing imaging so that noise is reduced. A photoelectric conversion unit configured to perform photoelectric conversion; a charge accumulation unit configured to accumulate charges obtained by the photoelectric conversion unit; a transfer unit configured to transfer the charges from the photoelectric conversion unit to the charge accumulation unit; a reset unit configured to reset the charge accumulation unit; a reset voltage control unit configured to control a voltage to be applied to the reset unit; and an additional control unit configured to control addition of capacitance to the charge accumulation unit are included. The charge accumulation unit includes a plurality of regions. The present technology can be applied to, for example, an imaging device that captures an image and a ranging device that performs ranging.

Image sensor, imaging device, and ranging device

The present technology relates to a light receiving device and a distance measuring module capable of improving sensitivity. A light receiving device includes a pixel array unit in which pixels each having a first tap detecting charge photoelectrically converted by a photoelectric conversion unit and a second tap detecting charge photoelectrically converted by the photoelectric conversion unit are two-dimensionally arranged in a matrix. The first tap and the second tap each have a voltage application unit that applies a voltage, the pixel array unit has a groove portion formed by digging from a light incident surface side of a substrate to a predetermined depth, and the groove portion is arranged so as to overlap at least a part of the voltage application unit in plan view. The present technology can be applied to a distance measuring sensor or the like of the indirect ToF scheme, for example.

Light receiving device and distance measuring module

An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.

Information processing apparatus, information processing method, and program

Disclosed herein is a sleep aid device including: an electrode arranged on the surface of a pillow in such a manner as to come into contact with the scalp of a user; a brain wave signal acquisition section adapted to acquire a brain wave signal of the user via the electrode; an analysis section adapted to analyze the acquired brain wave signal; and a control section adapted to control the execution of a preset process according to the sleep stage representing the depth of sleep of the user identified by the analysis result.

Sleep aid device and method, program and recording medium

An electroencephalographic headset includes: a supporter that includes expanding and contracting wires each having expansion and contraction properties and is to be attached to a head of a user by expansion and contraction of each of the expanding and contracting wires; and a plurality of electrodes that are provided to the supporter in defined placement.

Electroencephalographic headset

A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

Data transfer apparatus, data transfer method and processor

Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

Integrated circuit chip with modular design

Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

Methods and apparatus for supporting multiple configurations in a multi-processor system

The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memoryaccording to the translated physical address.

Information processing device, data transfer method, and information storage medium

Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.

Methods and apparatus for facilitating coherency management in distributed multi-processor system

Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; using the second portion of the first intermediate address to produce a second intermediate address; and using at least a portion of the second intermediate address as a pointer directly to one of the referenced entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

Methods and apparatus for address translation from an external device to a memory of a processor

Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Methods and apparatus for list transfers using DMA transfers in a multi-processor system

Growing community of inventors

Kanagawa, Japan

Yuji Suzuki