Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Murata Manufacturing Co., Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Acoma Medical Industry Co., Ltd

Yuji Shirai

Chiko Yorita

Mitsuaki Katagiri

Yu Hasegawa

Yasuo Osone

Kanji Otsuka

Yoshihide Yamaguchi

Toshio Hatada

Kenya Kawano

Seiichi Tomoi

Asao Nishimura

Akira Yamagiwa

Ichiro Anjo

Toshio Miyamoto

Hirokazu Nakajima

Yoshiyuki Kado

Takayuki Okinaga

Takao Ohba

Kunihiko Nishi

Akira Tanaka

Hitoshi Matsushima

Naotaka Tanaka

Kazuji Yamada

Hiroshi Inoue

Hiroyuki Nagai

Yoshihiro Kondo

Masatsugu Arai

Hiroshi Okabe

Munehisa Kishimoto

Masaki Ito

Akiomi Kohno

Tamotsu Usami

Chushiro Kusano

Koji Fujii

Michiharu Honda

Susumu Iwai

Hiroichi Shinohara

Satoru Konishi

Toshihiro Matsunaga

Hideki Uchida

Takashi Emata

Shizuki Nakajima

Osamu Horiuchi

Takehiro Ohnishi

Toshihiro Komatsu

Yasuyuki Yamasaki

Yoshihiro Kondou

Hitoshi Yoshidome

Kei Shimada

Shouji Matsugami

Toshihiro Tsuboi

Takashi Miwa

Makoto Omata

Tsuneo Endou

An anesthetic tank includes an insertion mouth for inserting an injection adapter of an anesthetic container, and a storage portion communicating with the insertion mouth. A volatile anesthetic inside of the anesthetic container is injected into the storage portion. An identifying member is arranged on the outside of the insertion mouth and is rotatable around the center axis of the insertion mouth. The identifying member has key groove formed in the internal surface of an insertion hole for inserting the injection adapter. The key groove are used for identifying the type of the volatile anesthetic in collaboration with keys formed in the injection adapter. A cover member has an opening formed in the position facing the insertion mouth and the insertion hole and presses the peripheral part of the identifying member.

Anesthetic tank, and system for preventing erroneous anesthetic injection

A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure COin a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.

Shielded electronic components and method of manufacturing the same

In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.

Semiconductor device and method of manufacturing the same

In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

Semiconductor device and manufacturing method thereof

Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.

Semiconductor device

A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.

Acoustic wave filter and manufacturing method of the same

A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.

A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Semiconductor device and manufacturing method of that

A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

Semiconductor integrated circuit device and its manufacturing method

Wafer level chip size package having rerouting layers

With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

Semiconductor device and a method of manufacturing the same

A molded semiconductor device has a plurality of slender leads formed with a sealing strip connecting them together to prevent the molding material from leaking out between the leads. Specifically, the sealing strip comprising an adhesive and an electrically insulating material is applied to the leads substantially perpendicular to the lengthwise direction of the leads. The strip is place such that an inner edge thereof substantially lies on a boundary line or inside where the molding terminates. The strip is then thrust into spaces formed between the leads. Thereafter the semiconductor chip is connected to the leads, the semiconductor chip and the leads are placed in a molding unit, the strip serving to block the molding material leaking outside the molding unit.

Method of fabricating a molded semiconductor device having blocking

A semiconductor circuit device includes a multi-layered substrate comprising a plurality of signal lines sandwiched between a power source line and a ground line, with insulation layers formed therebetween to reduce fluctuation of a ground line potential at the time of simultaneous switching of the signal lines and to increase the operational speed. The signal lines provides bidirectional current paths and is disposed between the current source line and the ground line. The multi-layered substrate is formed around a semiconductor pellet. Electrode pads are formed on the insulation layer over the ground line on the same level as the signal lines and generally on the same level as the main surface of the semiconductor pellet where electrodes pads are formed. Bonding wires are used to electrically connect the electrode pads on the pellet and the electrodes formed on the insulation layer. Additional bonding wires are used to electrically connect the electrode pads formed on the insulation layer and electrode pads formed on the power source line which is at a higher level and further away from the electrode pads formed on the insulation layer. Some of the electrode pads formed on the insulation layer is directly connected to the ground line using a side plate extension.

Semiconductor integrated circuit device

Disclosed is an LSI package cooling heat sink having a heat diffusion plate and thin wire fins joined to the heat diffusion plate. The heat sink is mounted on an LSI package and the LSI package is cooled by the flowing of fluid through the thin wire fins. The wire fins are made of a net formed of longitudinal thin wires intersecting with horizontal thin wires. The net is formed to continuous rectangular shapes or a swirl shape and joined to the heat diffusion plate. The net is constituted so that the number of the thin wires vertical to the heat diffusion plate is larger than the number of the thin wires parallel thereto and the net is joined to the heat diffusion plate by brazing, diffusion joint, pressure welding or the like. Since the heat sink is formed of the net composed of the longitudinal thin wires intersecting with the horizontal thin wires, the irregular portions of the adjacent thin wires are formed at a dislocated position and fluid striking against the thin wires produces many turbulent flows so that a high heat transfer performance can be obtained. Further, since the net formed of the thin wires is used, the size of cooling fins can be reduced and noise can be also lowered. Further, it is possible to produce an LSI package cooling heat sink in a short time which heat sink is excellent in mass-production.

LSI package cooling heat sink, method of manufacturing the same and LSI

Growing community of inventors

Hamura, Japan

Yuji Shirai