Fujitsu Corporation

Yuji Shirahige

Iwao Yamazaki

Hiroaki Kimura

Masaki Ukai

Aiichiro Inoue

Ryuichi Sunayama

Tsuyoshi Motokurumada

Kenji Fujisawa

An information processing apparatus includes a conversion buffer configured to store a conversion pair of a virtual address of a page and a physical address, a page table cache configured to store data in a page table at a level other than a last level and a physical address of the data in association with each other, a memory, and a processor coupled to the memory, and configured to store a hash of the virtual address and process management information of a conversion source in each entry of the page table cache, and when executing a maintenance instruction of deleting the conversion pair in the conversion buffer by specifying at least one of the hash of the virtual address or the process management information, delete an entry of matching at least one of the hash of the virtual address and the process management information, in the page table cache.

Information processing apparatus and control method

An arithmetic processor includes a request generation circuit which generates an information request including a request address. A translation buffer associates a virtual address of a page with a physical address (PA). A page-table buffer associates data in a page table in a level other than the last level with a PA of the data, and stores the associated data and address. A controller circuit obtains, from the request address, a PA of data in a page table to be accessed when the request address is not stored in the translation buffer. The controller circuit searches in the page-table buffer for the data when the page table to be accessed is in a level other than the last level. The controller circuit obtains the data from a memory, such as a cache memory or a main memory, when the page table to be accessed is in the last level, and registers the data in the translation buffer. The translation buffer may output an erase signal to invalidate all entries in the page-table buffer. The page-table buffer may include a control queue which outputs a control signal indicating a least recently used (LRU) entry.

Arithmetic processor, information processing apparatus, and control method of arithmetic processor

An apparatus includes: a cache to retain an instruction; an instruction-control circuit to read out the instruction from the cache; and an instruction-execution circuit to execute the instruction read out from the cache, wherein the cache includes: a pipeline processing circuit including a plurality of selection stages in each of which, among a plurality of requests for causing the cache to operate, a request having a priority level higher than priority levels of other requests is outputted to a next stage and a plurality of processing stages in each of which processing based on a request outputted from a last stage among the plurality of selection stages is sequentially executed; and a cache-control circuit to input a request received from the instruction-control circuit to the selection stage in which processing order of the processing stage is reception order of the request.

Arithmetic processing unit and control method for arithmetic processing unit

A processing device includes an instruction control unit outputting an instruction fetch request; a primary cache having a request port for the instruction fetch request and a cache processing unit that outputs instruction data for the instruction fetch request; and a secondary cache returning the instruction data to the primary cache. The request port has a primary port provided in common to threads and storing information on the instruction fetch requests of the threads, secondary ports provided for each threads, and each storing entry numbers of the primary port, and a request determination unit determining, from among the entered instruction fetch requests, an instruction fetch request to be input to the primary cache, with priority on an instruction fetch request waiting for being input to the primary cache, in an order of the instruction fetch requests of the respective threads that are output from the instruction control unit.

Arithmetic processing device and method for controlling arithmetic processing device

An arithmetic processing device includes: a arithmetic cores, wherein the arithmetic core comprises: an instruction controller configured to request processing corresponding to an instruction; a memory configured to store lock information indicating that a locking target address is locked, the locking target address, and priority information of the instruction; and a cache controller configured to, when storing data of a first address in a cache memory to execute a first instruction including locking of the first address from the instruction controller, suppress updating of the memory if the lock information is stored in the memory and a priority of the priority information is higher than a first priority of the first instruction.

Arithmetic processing device, arithmetic processing system, and method for controlling arithmetic processing device

A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.

Processor and method of control of processor

A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus. An address overflowed from a pre-fetch address queueis stored in the next-line pre-fetch control apparatus. An access address issued by a processor unit and stored in a registeris compared with the address stored in the next-line pre-fetch control apparatusand, if the two addresses are identical, a value obtained by adding a data block size &#x3bb; of cache memory to the address stored in the next-line pre-fetch control apparatusis stored again in the next line pre-fetch control apparatus. When the address issued by the processor unit is identical with that stored in the next-line pre-fetch control apparatusa predetermined number of times, the occurrence of continuous accesses is presumed and pre-fetching is carried out for all addresses that have not hit the pre-fetch address queue.

Pre-fetch control apparatus

The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

Pre-fetch control device, data processing apparatus and pre-fetch control method

In an information processsing unit with key controlled protection, since it takes a long time to fetch a storage key from key storage, an instruction and computation unit of a CPU receives data from a memory control unit of the CPU before a key is received, and then the transferred storage key is checked.

Growing community of inventors

Kawasaki, Japan

Yuji Shirahige