Socionext Inc.

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Yuji Sekiguchi

Yoichiro Miki

Yoshihiro Kishimoto

Tomoko Morita

Yasuaki Muto

Akio Niwa

Toshio Wakahara

Takuma Higashi

A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Method and apparatus for timing adjustment

In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to a delay selecting section. A selection part outputs, to a latch circuit, a delayed pulse signal obtained by delaying the latch pulse signal by the front delay circuit. The latch circuit delays the checking data piece from the memory at the reception of the delayed pulse signal. Then, the next data piece is read out from the memory and the selection part outputs, to the latch circuit, a delayed pulse signal delayed by the delay circuit at the preceding stage.

Data latch timing adjustment apparatus

Video data of a field necessary for I/P conversion and scanning line conversion is stored in a field memory part (), vertical frequency conversion is performed by a memory control processing part (), I/P conversion is performed by an I/P conversion processing part (), scanning line conversion is performed by a scanning line conversion part () and horizontal pixel conversion is performed by a horizontal pixel conversion processing part () with the data stored in the field memory part, and a synchronous processing part () supplies a prescribed clock, a horizontal synchronizing signal and a vertical synchronizing signal to each block. A single system performs vertical frequency conversion, I/P conversion, scanning line conversion and horizontal pixel conversion.

Video signal conversion device and video signal conversion method

Growing community of inventors

Nara, Japan

Yuji Sekiguchi