Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Yuji Satoh

Motoya Kanda

Hiroyuki Kobayashi

Jun Deguchi

Daisuke Miyashita

Takashi Kishi

Shouhei Kousai

Mototsugu Hamada

Yoshiyuki Isozaki

Hiromitsu Komai

Yutaka Shimizu

Fumihiko Tachibana

Junji Wadatsumi

Makoto Morimoto

Mitsuyuki Ashida

Takashi Toi

Yuta Tsubouchi

A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.

Semiconductor memory device

In a semiconductor integrated circuit, a first generation circuit generates a common mode voltage of a differential signal. A second generation circuit generates temperature information according to the common mode voltage. The temperature information is information corresponding to a characteristic of an amplifier circuit related to an ambient temperature. A correction circuit corrects a first reference voltage and a second reference voltage according to the temperature information. A comparator includes a first input node to which a first signal line is electrically connected; a second input node to which a second signal line is electrically connected; a third input node to which the corrected first reference voltage is input; and a fourth input node to which the corrected second reference voltage is input.

Semiconductor integrated circuit and receiver

According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

Semiconductor integrated circuit, receiving device, and control method of receiving device

A semiconductor integrated circuit includes a pair of differential signal lines including first and second signal lines, a first comparator, and a second comparator. The first comparator is configured to output at least one of a first signal corresponding to a difference between a potential of a first input node and a potential of a second input node, and a second signal corresponding to a difference between a potential of a third input node and a potential of a fourth input node. The second comparator is configured to output at least one of a third signal corresponding to a difference between a potential of a fifth input node and a potential of a seventh input node, and a fourth signal corresponding to a difference between a potential of a sixth input node and a potential of a eighth input node.

Semiconductor integrated circuit, receiving device, and communication system

According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Transmitter and receiver

The voltage to current converter according to the present embodiments includes a charge transfer device, a smoother and a current generator. The charge transfer device accumulates charge corresponding to an input voltage, and transfers the accumulated charge. The smoother accumulates the transferred charge to smooth an output voltage. The current generator generates a current corresponding to the input voltage by use of a current corresponding to the charge accumulated in the smoother.

Voltage to current converter

Equipment having a noise elimination function according to embodiments includes a signal generator configured to generate a signal in which a noise component other than thermal noise is discretely included, a noise detecting unit configured to detect the noise component other than the thermal noise discretely included in output of the signal generator, and a signal correcting unit configured to eliminate the noise component detected by the noise detecting unit from the output of the signal generator, and generation of noise other than thermal noise is detected, and a signal from which noise is reliably eliminated is generated.

Equipment having noise elimination function, PLL circuit and voltage/current source

An oscillator includes first, second, and third current sources, a resistor having first and second terminals, first and second capacitors each having first and second terminals, a switch circuit through which each of the current sources is connectable to the first terminal of one of the resistor and the two capacitors to supply current thereto, a comparator, and switch controller configured to generate control signals for the switch circuit and an oscillation output signal for each of multiple periods based on an output signal from the comparator. During one of the periods, the switch circuit is controlled to connect the first current source to the first terminal of the first capacitor, the second current source to the first terminal of the resistor, the first terminal of the resistor to a first input of the comparator, and the first terminal of the first capacitor to a second input of the comparator.

Stable oscillator for use in an electronic circuit

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

Oscillation frequency adjusting circuit

According to one embodiment, a reference signal generating circuit includes a first nonlinear element that generates a first reference voltage, a second nonlinear element that generates a second reference voltage, a current controlling circuit that controls a current flowing to the first nonlinear element and a current flowing to the second nonlinear element based on an output voltage of the current controlling circuit itself, and N temperature characteristic adjusting elements (N is an integer of 2 or larger) that individually adjust the temperature characteristics of the output voltage of the current controlling circuit.

Resistance signal generating circuit with n temperature characteristic adjusting elements

One embodiment provides a reference current generation circuit. The circuit has first and second reference current generation circuits for generating first and second reference currents respectively, and a current output circuit for outputting a third reference current by adding the first and second reference currents. The first reference current generation circuit includes first and second current-voltage conversion circuits and a first current supply circuit. The first current supply circuit provides substantially equal amounts of current to the first and second current-voltage conversion circuits respectively. The second reference current generation circuit includes third to fifth current-voltage conversion circuits and a second current supply circuit. The second current supply circuit provides a current to the fourth current-voltage conversion circuit, divide and provide amounts of current substantially equal to that of the current provided to the fourth current-voltage conversion circuit, to the third and fifth current-voltage conversion circuits respectively.

Reference current generation circuit

A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.

Semiconductor integrated circuit device and oscillation frequency calibration method

A semiconductor integrated circuit includes a ring oscillator and a noise canceller. The ring oscillator includes first and second signal generators. The first signal generator is configured to generate a first output signal having a first phase based on an input signal. The second signal generator is configured to generate a second output signal having a second phase different from the first phase based on the input signal. The noise canceller includes first and second amplifiers and an arithmetic module. The first amplifier is configured to amplify the first output signal generated by the first signal generator using a first amplification factor. The second amplifier is configured to amplify the second output signal generated by the second signal generator using a second amplification factor. The arithmetic module is configured to combine the first output signal amplified by the first amplifier with the second output signal amplified by the second amplifier.

Semiconductor integrated circuit and radio communication apparatus

A battery pack including: a nonaqueous electrolyte secondary battery including an external connection terminal; and a discharge control mechanism which controls discharge of the nonaqueous electrolyte secondary battery when a surface temperature of the nonaqueous electrolyte secondary battery exceeds a discharge control temperature T(&#xb0; C.) represented by&#x2003;&#x2003;(1)where Tis an ambient temperature in a range of 0 to 60&#xb0; C., Q is 8 (&#xb0; C./C), and A is a discharge rate (C) of the nonaqueous electrolyte secondary battery in a case where a current required for discharging a nominal capacity of the nonaqueous electrolyte secondary battery in one hour is 1C, and is within a range of 4C to 7C.

Battery pack with a discharge control mechanism

An overdischarge preventing circuit apparatus according to this invention is an overdischarge preventing circuit apparatus for a nonaqueous electrolyte secondary battery, including a discharge control mechanism which controls discharge of the nonaqueous electrolyte secondary battery when a surface temperature of the nonaqueous electrolyte secondary battery exceeds a discharge control temperature T(&#xb0; C.) represented by&#x2003;&#x2003;(1)where Tis an ambient temperature (&#xb0; C.), Q is 8 (&#xb0; C./C), and A is a discharge rate (C).

Overdischarge preventing circuit apparatus for a nonawueous electrolyte secondary battery, overdischarge preventing circuit apparatus for a battery pack, secondary battery overdischarge preventing method and overdischarge preventing method for a battery pack

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Kawasaki Kanagawa, Japan

Yuji Satoh