Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Yuji Saeki

Satoru Watanabe

Teruo Tanaka

Yoshiko Yasuda

Takayuki Nakagawa

Takashige Baba

Tatsuo Higuchi

Tadaaki Isobe

Shigeo Takeuchi

Junji Nakagoshi

Tatsuru Toba

A phase classification model of a cloud application deployment device calculates a feature vector for each time period from resource usage data for each time period when an application is executed, clusters the feature vectors for each time period, and validates a result of the clustering to determine which phase the feature vector belongs to. Validation between a feature vector of a new application and a feature vector belonging to a cluster of a known phase is performed, and it is determined whether each time period belongs to the known phase or an unknown phase on the basis of a degree of the validation. The resource usage of a computer node for each phase is inferred, and application deployment is performed on the basis of an inference result.

Cloud application deployment device and cloud application deployment method

The prefetch control is optimized according to a data pattern. The model selection unit selects inference units from outside of the device driver and replace each of the inference units according to the type of data analysis. The inference units, each of which is a neural network, predict an address region of the SSD based on I/O trace data collected by the device driver and instruct the device driver to prefetch from the outside based on the prediction result. The prefetch execution unit performs prefetch for the storage cache allocated to the SCM based on the prediction by a neural network associated with the query and the database.

Data processing device, storage device, and prefetch method

An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.

Data processing apparatus and prefetch method

A computer system, comprising a plurality of computers, each of the plurality of computers including at least one processor chip each including a plurality of processor cores, the at least one processor chip constructing a plurality of regions each constructed by at least one processor core, each of the plurality of processor cores carries out calculation processing for executing a predetermined program and inter-core communication processing, which is communication between the plurality of processor cores, the computer system comprising: a regulation module which controls a voltage and a frequency that are supplied to each of the plurality of regions; and a determination module which determines a power mode of each of the plurality of regions, to output an instruction to the regulation module.

Power saving for a computer system and computer based on differences between chip regions in processing and communication times

An information processing apparatus includes a processor, a plurality of storage devices, and an FPGA. The plurality of storage devices stores a plurality of items of segment data. Each item of segment data includes configuration information on a configuration of the segment data. A search command in which search target segment data and a search formula for the database are described is received from a host computer. The FPGA reads the configuration information relating to the search target segment data, analyzes the search formula to specify column data to be used for search, specifies, based on the read configuration information, a storage location of the specified column data in the search target segment data, reads column data to be used by the specified search target from the storage device in which the search target segment data is stored and executes search, and returns the search result to the host computer.

Information processing apparatus, processing apparatus, data search method

In a data transmission and reception system, a reception-side unit determines a phase adjustment of received relative to a local clock. The reception-side unit includes a means for computing an optimum delay time based, among other data, on externally provided values which are stored locally. In an alternate embodiment of the invention, a transmission-side unit includes a similar mechanism.

Phase-adjustment control method and information processing apparatus

In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.

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Tokyo, Japan

Yuji Saeki